Spiking Neural Networks (SNNs) leverage discrete, event-driven processing to achieve exceptional energy efficiency through intrinsic bit-sparsity. While current SNN accelerators effectively reduce latency by skipping zero-valued spikes, they often overlook the structural redundancy present in spatially adjacent activation patterns, or rely on expensive global search mechanisms to exploit it. We observe that neighboring spike rows frequently exhibit high similarity due to spatial locality. To exploit this efficiently, we introduce Differential Spike Encoding (DSE) , a logic-driven paradigm that decomposes adjacent rows into a shared Base Vector and sparse Differential Vectors . We present Comperity , a specialized hardware accelerator that implements a stateless, index-driven dataflow . By replacing complex pattern matching with lightweight AND/XOR logic arrays, Comperity significantly reduces arithmetic redundancy with negligible control overhead . Experimental results demonstrate that Comperity achieves speedups of 1.62× , 9.0× , and 2.3× over state-of-the-art SNN accelerators Prosperity, PTB, and the A100 GPU on SpikeBERT projection layers, respectively. Moreover, Comperity improves geometric mean energy efficiency by 1.35× , 10.7× , and 270× , respectively. Finally, analytical comparisons confirm that Comperity remains within a competitive range in per-synaptic-operation energy against event-driven neuromorphic platforms (e.g., Loihi and TrueNorth), providing a high-throughput and energy-efficient solution for edge neuromorphic computing.

Brain-inspired spintronic artificial neural networks (ANNs) have emerged as promising candidates for next-generation computing systems, yet conventional spin-orbit torque (SOT) devices face challenges of high current density ( 1011 - 1012 A/m2) and Joule heating-induced variability. Here, we introduce orbit torque (OT) derived from light metal Ti (effective orbit Hall angle approximate to 0.4 ) to drive ferromagnetic synapses and neurons with a biologically inspired continuously differentiable exponential linear unit (CeLu) activation function. We systematically characterize device variations, including cycle-to-cycle (CTC) and device-to-device (DTD) fluctuations, and reveal that Joule heating significantly contributes to CTC variability through finite element and micromagnetic simulations. Optimizing the neural network depth reduces error propagation induced by CTC variation. Moreover, the network exhibits higher tolerance to DTD variations compared to CTC variations. Our OT-driven all-spin ANN achieves a recognition accuracy of 90.1 +/- 0.2 % on the MNIST dataset under combined synaptic and neural CTC and DTD variations. This work provides a viable path towards low-power neuromorphic computing systems by leveraging OT's advantages of reduced thermal dissipation and stable switching characteristics.

The demand for real-time streaming graph analysis has grown significantly, as hundreds of thousands of updates come every second. Monotonic graph algorithms such as Shortest Path are widely used in real-time analytics, but there are two bottlenecks that limit their performance, specially on planar graphs. One is massive redundant data accesses due to irregular state propagations and the other is high memory latency caused by irregular data accesses. We observe that existing systems mainly focus on general-purpose graph algorithms. If the properties of specific graph algorithms are exploited, the analysis performance can be further improved. Moreover, these systems typically tackle these two bottlenecks separately through either software or hardware mechanisms, but not both. However, both bottlenecks need to be addressed simultaneously in real scenarios such as road navigation. This article proposes WSGraph, a software-hardware co-design framework for high-performance streaming graph processing. WSGraph tackles these two challenges by enforcing regularized processing orders and enabling precise data prefetching. Specifically, at the software level, WSGraph integrates a priority-based work scheduler with sliding-window bucket mapping scheme to regulate state propagations, thereby drastically reducing redundant data accesses. At the hardware level, WSGraph incorporates a lightweight in-core Proactive Data Engine (PDE). By exploiting intra-vertex access regularity, the PDE accurately prefetches relevant graph data to effectively hide the high latency of irregular memory accesses. Experimental results demonstrate that WSGraph achieves significant performance improvements over existing systems. Compared with the state-of-the-art software system KickStarter, WSGraph gains a 2.13× speedup primarily by reducing graph data accesses by an average of 78.6%.

ABSTRACT The human brain can construct coherent spatial imagery in the absence of sensory input—an “imagination” capability that complementary metal‐oxide‐semiconductor transistor (CMOS)‐based artificial neural networks (ANNs) struggle to replicate with comparable energy efficiency and architectural compactness. Realizing this function in hardware requires a single spintronic device that simultaneously provides field‐free switching and intrinsic, Gaussian‐distributed stochasticity; yet such devices have not been reported to date. Here, we report field‐free spintronic neuromorphic devices that exploit the spin‐splitting effect of altermagnetic RuO 2 . The resulting stochastic neuron exhibits Gaussian‐distributed outputs, which reduces the number of devices required by about 87%. Benefiting from the high thermal conductivity and micrometer footprint of RuO 2 , transient Joule heating drives stochastic, field‐free magnetization reversal in the adjacent Co/Pt multilayer. Leveraging these devices, we implement an all‐spin ANN to restore CIFAR‐10 images with 50% occlusion. The reconstructed images achieve a high Fréchet Inception Distance score of 1.98 and a classification accuracy of ∼90%, and a 3.75‐fold improvement in recognition performance. Our work establishes an energy‐efficient, hardware‐level pathway toward brain‐inspired imagination systems, advancing the functional emulation of cortical associative processes.

The proliferation of third-party Intellectual Property cores in Integrated Circuit design has introduced significant security risks, particularly the threat of hardware Trojans (HTs). Existing HT detection methods based on single-gate granularity analyze individual gate attributes but overlook the multi-gate structure of HTs, leading to excessive false positives and heavy manual verification. Comparatively, full-netlist analysis methods, while comprehensive, suffer from poor locating precision and scalability issues in large-scale netlists. Subgraph-based approaches aim to overcome these limitations but often rely on non-feature-based, non-collaborative techniques such as random sampling, to build subgraphs, incurring high computational overhead and low detection accuracy. To address these challenges, we propose SubG4TJ, a collaborative subgraph-based framework that integrates intrinsic gate attributes with structural connectivity for accurate and efficient HT detection. SubG4TJ identifies a specific class of gates-termed Less-Toggle Gates (LTGs)-that exhibit asymmetric 0/1 controllability, and introduces a concealment-based metric to quantify this property. By combining this intrinsic indicator with inter-gate structural features that capture Trojan interconnectivity, SubG4TJ enables targeted subgraph extraction centered on LTGs, substantially reducing analysis scope. A graph neural network then jointly model nodes' concealment attributes and subgraphs' topology features, enabling collaborative and end-to-end classification of suspicious subgraphs. This joint modeling of controllability asymmetry and structural connectivity allows SubG4TJ to effectively balance detection accuracy, false positive suppression, and runtime scalability. Evaluations in various benchmark circuits demonstrate that SubG4TJ improves true positive rate by up to 13.6% and achieves a speed-up of 120x, with performance gains increasing in larger designs.

Combinatorial optimization problems (COPs) hold significant application value in logistics, chip design, resource allocation and so on. Ising machines demonstrate unique advantages in solving COPs through physical annealing processes. However, existing Ising architectures face two key challenges: first, current annealing strategies struggle to balance parallelism and solution quality, with existing parallel annealing methods often trapped in local optima while conventional serial methods exhibit prohibitively slow convergence; second, the hardware overhead of spin update circuits scales linearly with spin count, resulting in low spin integration density. To address these challenges, we propose three key innovations: a novel Dynamic-ratio Parallel Annealing (DPA) strategy that dynamically adjusts spin flip ratios during the annealing process while preserving solution quality and significantly improving convergence speed, an approximate computing approach using 8-bit segmented adders that maintains computational accuracy while significantly reducing hardware complexity, and a hardware-optimized hard- σ method that further simplifies probability flip calculations by replacing exponential operations with addition-based approximations. Comprehensive evaluations show Approximate Computing based Ising Machine with Dynamic-ratio Parallel Annealing (ACIM) achieves 10–100 × faster convergence than baseline approaches with only 0.54

In safety-critical systems such as autonomous driving and aerospace, memory reliability standards are evolving from "high-reliability" to "ultra-reliability," demanding the eradication of all foreseeable, deterministic failure modes. To address the prevalent challenge of Double Adjacent Errors (DAE) induced from radiation, the design of SEC-DED-DAEC codes faces a critical dilemma: efficient but flawed Hsiao-based codes that risk miscorrection, versus correct-by-construction but costly and inflexible OLS-based codes. This trade-off between efficiency and correctness presents a key barrier to designing ultra-reliable systems. To resolve this impasse, this paper introduces MCTS-CDB, a novel Computer-Aided Design (CAD) framework. By integrating a CDCL-inspired search with Monte Carlo Tree Search (MCTS) guidance, it systematically constructs codes that achieve a zero-miscorrection guarantee within the highly-efficient Hsiao architecture. Experimental results validate our approach, showing that compared to a wide range of existing schemes, our generated codes achieve the correctness while reducing average encoding and decoding delays by 24.15% and 13.66%. This work provides a practical solution for designing the ultra-reliable memory subsystems required by next-generation safety-critical applications.

This work proposes a modeling methodology for simulating total ionizing dose (TID) effects in bulk FinFETs. The primary objective is to achieve congruence between the simulated I-D-V-G curves and experimental results under multiple conditions. Based on a model capable of reproducing the electrical characteristics of the device before irradiation, further calibrating defect-related parameters and source/drain depth that affect the model's accuracy under multiple bias conditions enables a closer match between the simulation results and the postirradiation experimental data. The simulated preirradiation I-D-V-G curves were calibrated through systematic optimization of the channel length, doping profiles, work function, and source/drain series resistance. For postirradiation characteristics, the accuracy of the model was improved by adjusting the density of oxide-trapped charges and interface traps, along with the distribution of interface traps and the source/drain depth. The I-D-V-G curves measured at multiple drain biases were employed to calibrate the model, enabling the final simulation results to become as close as possible to the characteristics of the practical device.

In harsh environments like space, multiple cell upsets severely threaten the reliability of on-chip memories. While single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are effective against adjacent double-bit errors, a critical challenge remains: many existing implementations are prone to miscorrecting certain non-adjacent double-bit errors, creating a reliability vulnerability. Furthermore, current solutions often suffer from poor scalability or significant hardware overhead. This paper addresses these challenges by proposing a novel SEC-DED-DAEC algorithm that guarantees a zero error rate for all double-bit errors. The proposed algorithm is highly scalable, capable of generating optimized check matrices for data widths ranging from 8 to 512 bits. Through a systematic construction and optimization process, our approach not only eliminates miscorrection but also reduces redundancy. Compared to state-of-the-art zero-errorrate SEC-DED-DAEC schemes, our method requires fewer check bits, demonstrates superior scalability, and as verified by hardware synthesis, results in lower area, latency, and power consumption in its encoder and decoder circuits.

Modern General-Purpose Graphics Processing Units (GPGPUs) leverage massive Thread-Level Parallelism (TLP) to hide memory and computation latencies. However, static scheduling policies, such as Round-Robin (RR) or Greedy-Then-Oldest (GTO), struggle to adapt to the dynamic pressure on execution units, leading to unbalanced resource utilization. Existing schedulers typically overlook the congestion status of backend units (e.g., ALU and Load/Store Unit) and fail to exploit the instruction type information available at the frontend. This oversight can cause schedulers to issue instructions to already congested units, inducing pipeline stalls while leaving other units idle. To address this, we propose RPAWS (Resource-Pressure Aware Warp Scheduler). RPAWS employs an I-Buffer lookahead mechanism to identify the next instruction type (Compute vs. Memory) for each warp, dynamically classifying warps into a compute queue or a memory queue. Simultaneously, it monitors the realtime busyness of backend units and dynamically adjusts the priority of these queues: prioritizing the compute queue when the memory unit is congested, and vice versa. Experimental results demonstrate that RPAWS improves performance by an average of 22.7% and reduces pipeline stalls by 19.7% compared to the baseline. Furthermore, RPAWS requires only minimal additional storage and logic.

Function secret sharing (FSS) has become a core primitive in privacy-preserving computation. However, each FSS invocation requires a fresh pair of function keys generated by a trusted dealer , expands the system's trust boundary and hinders practical deployment. Existing dealerless protocols eliminate this dependency, but incur substantial communication and a number of interaction rounds that grows linearly with the input bit-width, making key generation a major bottleneck. This paper present KORD, a protocol–hardware co-design that dramatically reduces the cost of dealerless FSS key generation. At its core is a pair of special-purpose chips that establish a common root of trust through mutual attestation and, within it, reconstruct FSS keys—eliminating the need for a dealer. This root of trust further forms a security boundary within which KORD restructures the generation protocol, collapsing the interaction of prior dealerless protocols into a single round, independent of GGM depth. A cross-key scheduling scheme then interleaves independent GGM-tree traversals, sustaining high computational throughput. KORD reduces per-key-generation communication by 7,633–70,274× over the state-of-the-art distributed FSS protocol across a comprehensive suite of FSS building blocks. Post-route analysis projects 12.75 million 32-bit DPF keys per second at 204 MHz using 21.5K LUTs, with 99.8

Modern GPGPUs partition Streaming Multiprocessors into multiple sub-cores (SCs) to enhance throughput and energy efficiency. While each SC has its own scheduler and execution units, they contend for shared downstream resources like the L1 cache and the memory subsystem. We observe that the uncoordinated, locally-optimal decisions made by independent SC schedulers lead to synchronized bursts of memory requests, causing severe system-wide memory congestion. This results in long stall cycles and significant under-utilization of the SM’s execution units. Existing schedulers, which focus on optimizing for a single aspect like locality or application phase, lack the cross-SC coordination necessary to mitigate this fundamental architectural bottleneck. To address this, we propose CACWS (Congestion-Aware Coordinated Warp Scheduler), a novel framework that enables runtime coordination among SC schedulers. The cornerstone of CACWS is a low cost hardware mechanism, the congestion vector register, which provides each scheduler with a real-time view of the memory pressure from its peers. Upon detecting impending SM-wide congestion, a scheduler proactively shifts its local priority from memory-intensive warps to compute-intensive ones. This strategy enforces a staggered memory access pattern across SCs, effectively smoothing out memory request traffic and enabling better overlap of computation and memory latency. Furthermore, CACWS integrates this coordination with a multi-queue warp management policy that classifies warps based on their arithmetic intensity and locality characteristics. Evaluations across a representative suite of diverse workloads show that CACWS achieves an average performance speedup of 24.9%, illustrating its effectiveness in managing resources for modern partitioned GPU architectures.

With the advancement of 5G and the Internet of Things (IoT), traditional upper-layer authentication mechanisms are vulnerable to attacks, while quantum computing threatens cryptographic security. Radio frequency fingerprint identification (RFFI) offers a physical-layer solution by exploiting inherent hardware imperfections. However, in complex electromagnetic environments, narrowband and especially agile interference (characterized by low power and narrow bandwidth) can severely distort fingerprint features, rendering conventional detection algorithms ineffective. To address this challenge, this paper proposes a novel interference detection framework tailored for Orthogonal Frequency Division Multiplexing (OFDM) systems. First, a signal transmission model incorporating non-ideal hardware characteristics (e.g., DC offset, I/Q imbalance) is established. Based on this model, we design an agile interference detection algorithm comprising two key components: (1) a time-series anomaly detection method that fuses multi-domain expert features (fractal, complexity, and high-order statistics) with machine learning, demonstrating superior performance over the traditional CME algorithm under narrowband interference, and (2) a progressive search segmental detection algorithm that, combined with reconstruction error features extracted by an autoencoder, effectively identifies low-power agile interference by appropriately trading-off computation time for detection sensitivity. Finally, an OFDM simulation platform is developed to validate the proposed methods. The results show that the segmental detection algorithm achieves reliable detection at a jammer-to-signal ratio (JSR) as low as -10 dB, significantly outperforming existing approaches and enhancing the robustness of RFFI in challenging interference environments.

The simulated annealing (SA) algorithm is a widely used reference method for iterative Ising annealers, but its sequential spin updates restrict parallelization and lead to slow convergence in large fully connected systems. Parallel annealing algorithms accelerate convergence by updating multiple spins simultaneously, but this requires evaluating spin-flip probabilities for all spins at every step, leading to redundant computations and substantial hardware demand. We introduce Self-Adaptive Pruning and Parallel Annealing (SPPA), a parallel algorithm that incorporates spin inertia through a candidate spin set to reduce unnecessary probabilistic spin-flip computations. SPPA achieves convergence speed comparable to state-of-the-art methods while improving solution accuracy by 0.9%–7.8%. Furthermore, by pruning redundant evaluations, SPPA reduces the number of required spin update units (SUUs) by up to 75%.

This paper presents a charge pump phase-locked loop (PLL) with an input range of 1 MHz to 1.2 GHz and an output frequency range of 16 MHz to 3.5 GHz. The proposed design employs global self-bias and bandwidth-adaptive techniques, eliminating the need for large bias circuits and reducing power consumption. The circuit is implemented using both planar technology and fin field-effect transistor technology, demonstrating high stability and compatibility in both system-synchronous and source-synchronous applications through experimental validation.

This paper quantitatively discusses the influence of well contact on Single Event Transient (SET) in sub-20 nm FinFET by Two-Photon Absorption (TPA) pulse laser. Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process. The experimental results show that the SET pulse width has a bimodal symmetric distribution, which is different from that of a bulk planar CMOS device. To investigate the detailed mechanism of the phenomenon, a high-precision FinFET TCAD model was established, in which both Id-Vd and Id-Vg errors were less than 10% compared to the SPICE model provided by the commercial process. TCAD simulation under heavy ion injection showed the mechanism of the abnormalphenomenon, where the well contact plays a major role in charge collection at the near-well contact distance, while the source plays a major role at the far distance. This phenomenon is completely different from that of planar CMOS devices. This indicates that the SET mechanism becomes more complicated during the FinFET process. Therefore, more effective SET hardening methods should be investigated for FinFET.

Ising machines offer a promising hardware solution to combinatorial optimization problems but still face scalability and cost challenges. In this work, we present IDIM, an in-situ DRAM-based Ising machine that exploits in-memory computing within DRAM subarrays to enable large-scale, fully connected spin updates with lightweight hardware overhead. By introducing lightweight logic into sense amplifiers and redesigning an in-memory DRAM adder, IDIM minimizes data movement and significantly improves area utilization. Prototyping results show that IDIM achieves over 166× speedup in annealing time compared to conventional computational substrates, while the additional peripheral circuitry only accounts for 3.6% of the baseline area.

Network-on-Chip (NoC) is widely used for on-chip communication in System-on-Chip designs. Application mapping, a key design step, aims to improve NoC performance. As design demands become more sophisticated and scales expand, existing application mapping optimization methods lack multi-objective optimization capabilities to support flexible design and struggle to ensure both effectiveness and efficiency in large-scale implementations. In this paper, we propose a multi-objective application mapping optimization strategy for large-scale NoC designs, which employs a MILP-based method to obtain mappings that meet diverse requirements of high throughput, low latency and low power consumption. Additionally, the strategy integrates a pruning method using heuristic partitioning and pre-mapping techniques to reduce the search space efficiently while preserving solution quality, thereby balancing computational efficiency with solution effectiveness. Experimental results show that the mappings generated by this strategy outperform both randomly generated mappings and those generated by advanced methods under both low-communication-cost and high-throughput scenarios. Moreover, the strategy balances efficiency and effectiveness in large-scale designs, demonstrating excellent scalability.

Transformers have achieved remarkable success across AI domains, but they face a quadratic complexity bottleneck in attention with respect to sequence length. Dynamic sparse attention methods reduce this cost but suffer from irregular sparse patterns and hardware inefficiency. To address these issues, this paper proposes DARS (Dynamic Attention with Regularized Sparsity), an algorithm-hardware co-design framework for attention acceleration. Algorithmically, we propose a dynamic adaptive hierarchical Top-K pruning method that partitions attention rows into fine-grained groups and assigns adaptive sparsity levels. This process inherently forms regular sparse structures while preserving model accuracy. Architecturally, we design a dual-engine architecture comprising a Dynamic Pruning Engine (DPE) and a Sparse Attention Computing Engine (SACE). The DPE employs low-precision computation for pruning and index generation, while the SACE performs high-precision attention computation on the selected positions. By decoupling dynamic prediction from sparse computation, DARS enables end-to-end optimization. Experimental results demonstrate that DARS achieves a high sparsity of 77.7–91.6% on BERT models with no accuracy degradation; on Bloom models, it reaches 90.3–91.2% sparsity while maintaining perplexity (PPL) consistent with the baseline. Furthermore, DARS significantly outperforms GPUs and state-of-the-art accelerators such as SpAtten and Sanger in terms of throughput.

The emerging technologies of 3D chiplet integration offer a promising path to increase functional density and communication efficiency beyond the limitations of traditional 2D designs. Among various methods, hybrid bonding enables high-density vertical connections with reduced parasitics and latency. However, few existing approaches explicitly support this vertical interconnect scenario, and most treat partitioning and floorplanning as separate stages. To fully exploit the benefits of vertical integration, partitioning and floorplanning need to be considered jointly to balance bond demand and bond supply. In this paper, we propose a unified framework for 3D chiplet partitioning and floorplanning under fine-pitch bonding technologies. Experiments on industry-standard benchmarks demonstrate a 10%∼40% reduction in HPWL and over 60% decrease in inter-die vertical connection overflow, confirming the effectiveness and superiority of our approach over current methods.