The inherently limited short-circuit (SC) withstand capability of silicon carbide (SiC) MOSFETs poses a critical reliability bottleneck for high power applications, and this paper addresses this challenge by first revealing a universal SC current trend of initial rise followed by decline, then establishing a key correlation that the time to reach peak SC current (tpeak) is linked to the device's zero-temperature coefficient voltage (VZTC), where a smaller VZTC shortens tpeak and enables earlier current decline and better SC withstand capability. To reduce VZTC from 18.7 V to 10.3 V, here three device structural optimizations are proposed: channel shortening, a redesigned two-layer P-well, and optimized current spreading layer concentration. These optimizations work by adjusting the proportional contributions of the device's resistive components. The channel resistance and neck resistance have negative temperature coefficients while the drift region resistance has a positive temperature coefficient, and the proportion adjustment modifies VZTC. Using these optimizations, SiC MOSFETs were fabricated and tested. SC experimental results under a 600 V bus voltage validate the proposed strategy. The optimized device exhibits a significantly shortened tpeak, with its SC withstand time extended from 6.9 mu s to 8.0 mu s and its SC withstand energy improved from 0.216 J to 1.12 J. Notably, these reliability enhancements are achieved without degrading the on-state resistance or breakdown voltage, thus providing a novel trade-off-free approach to enhance the short-circuit reliability of SiC MOSFETs.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with conventional thermal SiO2 gate oxides are plagued by issues such as low channel mobility, threshold voltage instability, and premature oxide breakdown. To address these challenges, high-kappa dielectrics, specifically aluminum oxynitride (AlON) with a SiO2 interlayer, have been employed to mitigate electric field effects and improve interface properties. In this work, AlON/SiO2 stacks with tunable nitrogen doping ratios were fabricated via plasma-enhanced atomic layer deposition. An analytical method for extracting the flat-band voltage and quantifying fixed interface charges is presented, which remains unaffected by interface states or oxide traps. Optimized in situ N-doping (10.37%) minimizes the fixed charge density at the AlON/SiO2 interface to -4.16 & times; 1012 cm-2. Based on calculations from MOSCAPs data, this controlled charge engineering enables precise tuning of the threshold voltage in SiC p-MOSFETs from -3.3 to -5.5 V, independent of process-induced variations. The study elucidates the role of nitrogen bonding configurations in governing interface charges and provides a reproducible strategy for their modulation, offering critical material-level insights for advancing SiC complementary metal-oxide-semiconductor (CMOS) technology.

Abstract The full exploitation of 4H-SiC for power electronics is hampered by an incomplete understanding of its dislocation networks. In this work, we present a 3D dislocation mapping approach using synchrotron X-ray section topography to overcome this limitation. With an optimized diffraction condition, we simultaneously image all dislocation types throughout a 350 μm-thick wafer. Subsequent 3D reconstruction decodes the crystallographic identity of every defect, including basal plane dislocations (BPDs), threading edge dislocations (TEDs), threading screw dislocations (TSDs), and threading mixed dislocations (TMDs), based purely on their intrinsic morphology. Quantitative metrology of the reconstructed volume reveals a distinct crystallographic inclination pattern of TSDs and TMDs, providing strong topological evidence for the interplay between the macroscopic physical vapor transport growth front and microscopic thermal stress relaxation via prismatic slip. This method establishes a high-throughput framework for systematic defect analysis in a single scan, transitioning crystal characterization from qualitative imaging to quantitative 3D metrology for next-generation semiconductors.

In the fabrication of power semiconductor devices, process-induced residual stress and macroscopic wafer warpage are critical factors affecting device yield and long-term reliability. However, conventional X-ray diffraction metrology often fails to obtain continuous microscopic lattice strain distributions on highly warped wafers due to the strict angular selectivity of Bragg diffraction, resulting in data loss manifested as discontinuous "zebra patterns". This study presents a high-fidelity metrology framework based on synchrotron grazingincidence X-ray topography (GIXRT) to quantitatively decouple microscopic lattice strain from macroscopic curvature in processed wafers. By leveraging the beam expansion effect and implementing a multi-azimuthal angular scanning strategy, we established a continuous mapping from angular measurement space to physical parameter space, effectively overcoming the sampling limitations of traditional topography. Experimental validation on a patterned 200 mm IGBT silicon wafer demonstrates that the system achieves pixel-level quantitative reconstruction, successfully resolving lattice expansions and corresponding deformations induced by ion implantation. This work provides a robust non-destructive evaluation framework for advanced semiconductor process control, offering significant improvements in strain sensitivity and spatial continuity over conventional methods.

This work presents a 650-V All-GaN cascode switch engineered for high-frequency, robust hard-switching operation. The proposed device substitutes the conventional low-voltage (LV) Si MOSFET in a GaN/Si cascode device with an enhancement-mode (E-mode) GaN HEMT, while retaining the original 650-V depletion-mode (D-mode) GaN die. A stacked flip-chip assembly and a printed circuit board (PCB) layout with anti-parallel current paths are employed to achieve a significant reduction in parasitic inductance through magnetic flux cancellation. Compared to the commercial GaN/Si cascode device, the proposed All-GaN device achieves a 55% lower input capacitance (CISS) and a 65% lower reverse-transfer capacitance (CRSS) at VDS = 400 V, leading to a 34% reduction in turn-off time and a 22% reduction in turn-on time during 400-V double-pulse tests with reduced VDS overshoot and reduced ringing. In addition, dynamic on-resistance (RON) measurements indicate a negligible increment, validating its superior robustness compared to conventional p-GaN HEMT solutions.

Threshold voltage (V-TH) instability induced by oxide and bulk defects remains a critical reliability concern for silicon carbide metal-oxide-semiconductor field-effect transistors (SiC mosfets) in high-power applications. Traditional characterization methods struggle to separate overlapping trap signatures from transient drain current measurements, limiting the ability to predict V-TH drift under realistic operating conditions. This article proposes a physics-informed sparse representation framework that couples multitemperature transient analysis to discriminate oxide and SiC bulk trap contributions to V-TH variation. By constructing an overcomplete dictionary from established trap models and enforcing cross-temperature continuity, the method resolves five distinct bulk traps (H1-H5) and extracts time constant spectra (TCS) of oxide traps at various gate biases. Experimental results on commercial 1200V SiC mosfets reveal that trap H2 (activation energy 0.631eV), associated with p-well implantation, dominates V-TH transients under short turn-off durations, while trap H4 (0.834 eV), linked to gate oxidation, critically impacts high temperature operation. Oxide traps exhibit voltage-dependent time constants that extend to near-DC regimes, causing persistent V(TH )shifts. The proposed method provides quantitative trap parameters essential for reliability qualification and physics-based lifetime modeling, enabling more accurate prediction of V-TH drift in power converters.

Abstract GaN vertical devices are promising for high-voltage applications due to their high breakdown voltage and compact footprint. To enhance voltage-blocking capability, advanced field termination structures are essential, often implemented through deep mesa etching. However, such aggressive etching processes introduce severe surface damage and trench-like defects at the etched interface. Subsequent dielectric deposition via chemical vapor deposition (CVD) to fill these trenches tends to result in significant interfacial leakage, adversely affecting the reverse leakage current and overall breakdown performance, particularly in small-area vertical architectures. In contrast, plasma-enhanced atomic layer deposition (PEALD) of silicon nitride (SiN x ) offers exceptional conformality, effective trench-filling capability, and precise thickness control, making it highly suitable for passivating etching-induced interfaces. This study systematically investigates mesa passivation techniques and their corresponding performance benefits in GaN vertical Schottky barrier diodes (SBDs). Experimental results indicate that devices passivated solely with plasma-enhanced CVD-SiN x exhibit steadily increasing leakage current with applied voltage, reaching 1 mA at approximately 100 V. In marked contrast, PEALD-passivated mesa-terminated vertical SBDs achieve a breakdown voltage of 430 V, with leakage current effectively suppressed to a minimum level of 10 −11 A, remaining stable until the onset of hard breakdown.

SiC MOSFETs face challenges in accurately analyzing the junction temperature distribution during short-circuit events. Existing methods for determining this distribution has been suffering from low resolution, convergence issues, and limited accuracy. In this paper, we propose a fast electro-thermal coupling model for SiC MOSFET chips during short-circuits. By incorporating the temperature effects on carrier mobility and threshold voltage, our model significantly extends the operating temperature range of the IDS (VGS, VDS, T) data-driven compact model. The temperature-independent electric field distribution, E(x,y,z), is calculated by TCAD simulation. With these results, we establish a power distribution function, P(x,y,z,T), which serves as the Joule heating source in COMSOL. This approach allows us to rapidly compute the chip temperature distribution and transient short-circuit current. Verification results show that our method reduces computation time to less than 20 minutes, achieves current prediction accuracy above 85% over various bus voltages, and accurately identifies the maximum thermal stress region that coincides with the experimentally observed short-circuit gate failure location.

High switching speed wide-bandgap (WBG) devices demand precise multi-scale electro-thermal modeling with high resolution to optimize design and enhance reliability. This paper proposes a unified multi-scale electro-thermal model based on the Physics-Informed Graph Neural Network (PIGNN). The PIGNN integrates multi-level physics into device mesh graphs and leverages the transductive capability of Graph Neural Networks (GNNs) to adapt to new geometries and biases without retraining, enabling over 5000x faster simulations of both static and transient electro-thermal responses compared to Sentaurus. Its validity in cell-level structural optimization is illustrated through the field-limiting ring design of GaN vertical devices. The framework is also extended to enable globally optimized SPICE parameter extraction for both SiC MOSFETs and GaN HEMTs. This model exhibits robust stability in converging to reliable solutions for both structural design and parameter extraction even with a wide range of initial parameters, thus addressing the inefficiencies and stability challenges of traditional methods.

p-GaN HEMTs are favored for bridge topology applications where they act as the freewheeling transistors to commute the current during the dead time. However, the iDS , vDS and vGS oscillations at this period are observed and may introduce EMI problems. In this paper, we have demonstrated the presence of the negative resistance effect in p-GaN HEMTs by small signal analysis and revealed the origin of the abovementioned oscillations. The negative resistance comes from the unique reverse conduction mechanism of p-GaN HEMT and strengthen the oscillation of the driving current iG . According to the derivation formula of the negative resistance, it can be reduced by paralleling a resistor between the drain and source of the freewheeling transistor. Thus, an anti-parallel lateral rectifier (LR) is monolithically integrated with the p-GaN HEMT to reduce the negative resistance. A synchronous buck converter was constructed to verify the effectiveness in a circuit-level application. The experiment results show that the negative resistance has a 11% reduction and the oscillation amplitude of the iDS is reduced by 60% with 1% chip area of LR. Meanwhile, the high switching speed of the p-GaN HEMT is not affected.

Magnetic integration effectively enhances the power density of LLC resonant converter through the integration of the resonant inductor and main transformer. Following the technical approach of utilizing inherent leakage inductance of the transformer, precise leakage inductance control becomes critical. In this paper, an accurate leakage inductance model for magnetic integrated planar transformers is proposed. A revised leakage inductance calculation formula is derived, enabling precise computation of air-gapped transformers. Based on the proposed model, a design flow of transformers with customized leakage inductance is proposed and applied to an LLC resonant converter. The resonant frequency accuracy reaches over 99%, demonstrating the precision of the proposed model as well as the feasibility of the design flow.

A comprehensive and in-depth evaluation of the dynamic characteristics of p-GaN high-electron-mobility transistor (HEMT) components featuring a floating substrate is carried out, contrasting with devices having a source-connected substrate in traditional applications. A thorough analysis reveals similar degradation patterns of both devices but varying degrees of dynamic performance deterioration under transient stress. Experimental results show that under 200-V V-DS,V-off stress, devices with floating substrates experience a V-TH shift of 2.6 V and R-on degradation of 30%, while those with source-connected substrates exhibit a V-TH shift of 1.15 V and R-on degradation of 7%. A proposed capacitance coupling model specific to floating substrates explains the suboptimal dynamic performance. The negative substrate voltage, induced by capacitor charge imbalances during OFF-state stress, is a key factor affecting device performance. Understanding the sequence of hole and electron capture, along with dynamic resistance variations, is crucial for maximizing the advantages of p-GaN HEMTs with floating substrates.

GaN HEMTs are extremely sensitive to the parasitic inductance of driving loop due to the short switching time and the low maximum allowed gate voltage. However, for conventional gate driver, it’s impossible to achieve high switching speed and low voltage overshoot simultaneously. In this paper, a dynamic gate driver with suppressed gate voltage overshoot is proposed. The dynamic three-stage switching process realized by the high-speed and low-speed branches enables fast charging/discharging during the first stage and low oscillation during the last stage. Therefore, the proposed dynamic gate driver achieves short switching time of 9.76 ns and low voltage overshoot of 0.60 V at the same time, which are reduced by 8.36% and 34.78% compared with the conventional gate driver. The switching loss of the buck converter with the proposed dynamic gate driver is reduced by 18.5% and the drain voltage oscillation during dead time is much reduced.

The p-doping region is an important component of SiC junction barrier Schottky (JBS) diodes, which affects the electrical characteristics such as forward voltage drop, reverse leakage current, and breakdown voltage of the device. In this work, the p-doping region structure has been designed and optimized by a regional segmentation method, including doping profile and structural dimensions. Detailed analysis of the impact of different structural dimensions and doping concentrations in the p-doping region on device performance has been conducted through TCAD simulations and verified by device fabrication. Three segmented p-doping regions with optimized gradient doping parameters has been proposed and achieves a high breakdown voltage of 1600 V, low leakage current of only 0.7 mu A, reduced forward voltage drop of 1.53 V, and almost zero reverse recovery time under different temperature conditions ranging from 25 degrees C to 175 degrees C. The fabricated devices exhibit excellent electrical performance and temperature stability, which show promise for mass production of SiC power applications.

A novel fin-gate p-GaN (FPG) HEMT is proposed to simultaneously increase threshold voltage (Vth) and improve dynamic performance of the p-GaN HEMT. The fin gate structure works as a normally-on p-channel MESFET between gate and source by forming a Schottky-type contact on sidewall and a source-connected Ohmic type contact on top of the fin. Thus, the V th can change with the shutdown voltage of the p-channel MESFET, which can be modulated by the doping concentration and width of the fin-p-GaN. By optimizing the fin structure, a high positive V th of 4V is achieved without transconductance and breakdown voltage degradation in this work. It breaks the restriction between V th and on-resistance for conventional p-GaN HEMT. The dynamic characteristics of the FPG HEMT are investigated by SPICE simulations. Owing to the well-grounded p-GaN through the normally-on MESFET, the recovery process of the dynamic shift in V th (Delta Vth) after on/off-state stress can be accelerated by two orders of magnitude. It means an imperceptible dynamic degradation and a great potential in high frequency application for the FPG HEMT.

The 1.7 kV 4H-SiC MOSFET which features optimized retrograded-profile ion implantation in the JFET regions (RG-MOS) is proposed and fabricated on the 4 inch wafers. The measured results quantify the benefits of the RG-MOS structure: simultaneous improvement in high-frequency figures of merit (HF-FOM) (R onx C GD) by 1.5x, HF-FOM (R on x Q GD) by 1.5x and Baliga figure of merit (BFOM = 4BV2/R on,sp) by 1.6x compared with the conventional MOSFET (CON-MOS). Unlike other reported complicated structures which need high-precise fabricating process, the proposed RG-MOS structure is compatible with the prior planar 4H-SiC MOSFET process, and is favorable for large-scale production.

High-performance broadband photodetectors (PDs) are crucial in various military and civilian applications. However, conventional near-infrared (NIR) PDs still face several inevitable self-limitations such as a finite light absorption range for silicon (Si) and large area array issues for InGaAs. In response to these challenges, this work proposes a high-performance and uncooled NIR PD with wide-band response and long-term stability, which is integrated by the PbS quantum dots (QDs)/three-dimensional graphene (3D-graphene)/Si heterojunction. The incorporation of nanostructures (3D-graphene) and interface engineering (PbS QDs) on Si efficiently modulates carrier transport, optimizes light absorption, and enhances photovoltaic conversion efficiency. The detection range of the as-proposed Si-based PD can be extended to 2200 nm. And even at this wavelength, the device exhibits high detectivity (6.8 x 10(10) Jones) and high responsivity (5.2 x 10(4) mA/W). Furthermore, the device demonstrates satisfactory reproducibility and long-term stability, holding significant promise in optical logic gate circuits and infrared imaging applications. This research unlocks the full potential of Si in NIR detection and underscores its considerable potential in the development of next-generation NIR imaging and integrated circuits.

The curvature effect poses a significant challenge to the field termination structure, particularly in wide-bandgap (WBG) semiconductors used in power electronics. This work proposes a curvature-adaption termination (CAT) that effectively mitigates the curvature effect, achieving a more uniform electric field distribution and maximizing the voltage endurance capability of wide-bandgap semiconductors. The field termination structure is segmented into two sections based on depletion depth: the completely depleted region (CDR) and the partially depleted region (PDR). The CAT structure, developed through a two-step method, aims to strike a harmonious balance between CDR and PDR designs. By widening the rings in the CDR region and adjusting the curvature of the depleted line in the PDR region, the CAT structure successfully alleviates electric field concentration without necessitating an increase in termination area. This innovative design ensures a more uniform electric field distribution and optimizes the voltage endurance capacity of GaN devices. When applied to GaN vertical devices, the proposed CAT structure enables the blocking voltage (BV) to reach 93% (1950 V) of the critical value of the ideal device cell while maintaining on-resistance (Ron) and avoiding additional process steps. Furthermore, the CAT structural design can be extended to other vertical GaN power devices, such as JBS and p-n diodes. With the incorporation of the CAT structure, the BV of the vertical GaN JBS and p-n diode reaches 93% (1950 V) and 92% (1930 V) of the critical value of the ideal device cell, respectively. These outstanding properties demonstrate that the proposed CAT structure has the potential to significantly improve WBG power electronics and serves as a promising candidate for further advancements in the field.

This paper presents a double-voltage short-circuit protection circuit for SiC MOSFETs with temperature compensation, where the gate voltage reference threshold value $(V_{ref1}(T))$ is relative to the switching-on Miller platform voltage and is temperature-dependent, and the blanking time for HSF is determined by the time of the gate voltage rise to $V_{ref1}(T)$ and is dynamically self-adaptive with the junction temperature to assure the short-circuit protection circuit trigger fast. This method can effectively reduce the peak value of overcurrent and protect the device quickly from short-circuit destruction. In double pulse tests, With the temperature-dependent $V_{ref1}(T)$ , HSF detection time is 80 ns at room temperature and 62 ns at 120 °C. HSF detecting time is reduced by 25 % compared to the fixed Vref1. The drain current at HSF detecting trigger point is 38.6 A, 25.6 A, and 48.4 A, respectively and the overcurrent peak value after the HSF detection trigger point is 88.9 A, 93.1 A, and 106.6 A, respectively, for the case of $V_{ref1}(25\ {}^{\circ} C), V_{ref1}(120\ {}^{\circ} C)$ and the fixed $V_{ref1}$ for 120 °C. The drain current at HSF detecting trigger point and the overcurrent peak value are reduced by 47 % and 12.71 % respectively for the case of $V_{ref1}$ (120°C) and the fixed $V_{ref1}$ for 120°C. For FUL detecting delay time, it is 69 ns for all junction temperatures. The proposed short-circuit protection method can quickly detect the HSF error, suppress the overcurrent at high junction temperatures, and improve the reliability of SiC MOSFETs.

Traditional thermally grown SiO2 gate oxide layers in SiC power MOSFETs are prone to breakdown, reduced carrier mobility, and threshold voltage instability. Replacing SiO2 with high-k gate dielectrics in SiC power MOSFETs reduces the electric field within the oxide and enhances the carrier channel mobility by incorporating a thin SiO2 layer, with the AlON film's low trap chargedensity further improving threshold voltage stability. The PEALD-grown AlON films, characterized by the presence of negative fixed charges, cause a positive shift in the flatband voltage, complicating the design of threshold voltages. This paper investigates the modulation of fixed charges in PEALD grown AlON films by nitrogen doping, reveal a linear increase in flatband voltage with effective oxide thickness. X-rayphotoelectron spectroscopy (XPS) shows that carbon impurities are concentrated at the SiO2/AlON interface, where nitrogen incorporation enhances the formation of C-N bonds, effectively suppressing interface charges. Nitrogen doping process adjustment impacts C-N bond formation proportion. Alternately introducing NH3 and O2 (not simultaneously) promotes it, increasing the proportion from 8.99% to 13.17%. This creates a better reaction environment, reducing side reactions and enhancing efficiency and selectivity. With an PEALD Alternating growth process, the negative fixed charge density is suppressed to $-4.16\times 10^{12}\text{cm}^{-2}$, and the flatband voltage hysteresisremains below 0.1V regardless of post-deposition annealing. The process-grown SiO2/ AlON stack exhibits exceptional passivation properties, with an AlON bandgap of 6.53 eV and an oxide breakdownfield strength of 9.8 MV/cm. Even at an equivalent oxide thickness of merely 15 nm, the leakage current density is reduced to the $\text{nA}/\text{cm}^{2}$ level.