A background calibration technique based on dither injection is proposed to eliminate inter-stage gain errors in pipelined successive-approximation-register (Pipe-SAR) analog-to-digital converters (ADCs). Unlike prior methods that suffer from lengthy convergence times, the proposed scheme rapidly extracts the error coefficient by injecting a pair of opposite-amplitude dither signals into the input path, allowing the calibration to converge within an extremely short period. Moreover, the calibration accuracy is insensitive to both the input frequency and the error amplitude, indicating favorable robustness of the calibration technique. The effectiveness of the proposed technique is validated by simulation results. For a 14-bit 100-MS/s Pipe-SAR ADC, the signal to noise and distortion ratio (SNDR) improves from 56.61 dB to 83.16 dB, and the spurious free dynamic range (SFDR) improves from 70.03 dB to 103.50 dB. The algorithm converges with only 1,000 samples, representing a significant improvement over previously reported works.

Series correlated level shifting (SCLS) is a novel switched-capacitor technique that enables true rail-to-rail performance. Compared to the traditional CLS, it optimizes toward either speed or accuracy by flexibly tuning the feedback factor and equivalent loop gain of the MDAC. A 16-bit 50 MS/s pipelined ADC was designed in a 180 nm CMOS process. Simulation results show that the ADC achieves 13.4 bits ENOB, 82.6 dBc SNDR and 82.8 dBc SFDR with a 24 MHz 1.78 Vpp input signal.

This paper proposes a 14-bit 750 MS/s energy-efficient pipelined analog-to-digital converter (ADC) used in MEMS LiDAR system for time-of-flight (TOF) measurement. In this work, a novel opamp sharing technique is presented based on splitting multiplexing digital-to-analog converters (MDACs), thereby increasing the duty cycle of the residue amplifier to 100 % and reducing its power consumption to 25 % compared to the traditional case. Besides, the capacitor sharing method is incorporated in the prototype between the first two stages for a considerable reduction in effective load capacitance to relax the power budget further. The ADC prototype was fabricated in a 28 nm CMOS technology with an area of 0.138 mm2. With an input frequency of 103 MS/s, it achieves 76.4 dB spurious-free dynamic range (SFDR), while consuming 153.6 mW from a 2.5 V power supply. Adopting our high power- and area-efficient pipelined ADC in LiDAR TOF system, the ideal ranging accuracy can potentially reach +/- 20 cm, along with such a high SFDR, which significantly enhances the precision of the resulting 3D point cloud imaging.

This paper proposes a foreground calibration method, which applies simulated annealing (SA) algorithm to the calibration of successive approximation register analog-to-digital converters (SAR ADCs). The capacitor weights are updated according to the performance metrics of the output codes, without necessitating any signal injection or modifying the analog structure of the SAR ADC. The methods of iterative and parallel solving, as well as variable searching step size are introduced into the SA calibration for adequate search. In addition, a multi- objective optimization strategy based on lexicographic optimization is used to take into account the performance of both signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The estimated capacitor weights are applied in the digital domain to calibrate the SAR ADC output codes. The effectiveness of this calibration method is verified by simulating a 12-bit SAR ADC model with 2-bit redundancy and calibrating a 16-bit, 500 kS/s SAR ADC with 4-bit redundancy fabricated in 180 nm technology. The simulation results show the significant improvements in both SNDR and SFDR, along with a notable enhancement in integral nonlinearity (INL). 512 sinusoidal signal samples are collected on testing platform to extract the capacitor weights that can further contribute to the calculation of the output codes. The experiment results show that the SNDR and SFDR are improved by 20.04 dB and 20.19 dB, respectively, while the INL are enhanced by nearly 16 LSB.

This paper presents an output capacitor-less LDO regulator (OCL-LDO) with high PSR and ultra-low quiescent current. The circuit utilizes a local feedback amplifier based BGR and a pseudo-dynamic biased error amplifier to improve its PSR. Hereinto, the modified super source follower solves the stability problem in the local loop and further reduces the output impedance. Furthermore, the nested miller compensation based on dynamic nulling resistor (DNR-NMC) is utilized to keep stable in the full load range. The transient enhancement circuit can reduce the overshoot and outshoot voltage by 68% and 35%, respectively. This design implemented in 180nm technology occupies an area of 0.132 mu m2 and provides a controllable output over a supply range of 2.5V-5V and the maximum output current is 100mA. The PSR is less than-75dB at 100Hz and-40dB at 10kHz with the load current of 100mA. Additionally, the line regulation and load regulation are 0.08%/V and 0.21%/A, respectively.

This work presents a novel method that combines a MEMS differential scanning calorimetry (DSC) characterization chip with in situ Fourier-transform infrared (FTIR) spectroscopy, addressing the limitations of using a single technique to study the crystallization behavior of Polyamide 6 (PA6). We developed a highly sensitive single-crystal silicon thermopile calorimetric chip with a power responsivity of 149.3 V/W-seven times greater than the state-of-the-art commercial-available MEMS DSC system (20 V/W). It also has a cooling time constant of 2.4 milliseconds, which is one-sixth that of commercial systems (12 milliseconds). These advancements enhance the sensitivity and speed of DSC characterization. The combination of in situ FTIR spectroscopy allows for real-time monitoring of structural changes during crystallization. Our technique reveals the hot and cold crystallization processes in PA6 and defines the specific conditions for each process, providing valuable insights for controlling PA6 crystallization during processing.

This pretreating and decoding circuit is characterized by high speed and low area. This letter presents the shortest subsequence extraction algorithm as well as redefined and simplified methodology for character detection within single stage, eliminating redundant combinatorial logic and function block. Parallel 8B/10B decoder with mixed structure of decoding and disparity check is also proposed effectively. The circuit, acting as a significant role in JESD204B controller for Gigabit transmission, has been implemented and verified on Xilinx VC707 development kit. This design can achieve lane rate for up to 18.3Gbps, with increase in frequency by 31% and decrease in area by 12% compared with typical architecture and the optimization of the key components is also greatly remarkable.

In this paper, a smart system monitoring sensor based on a 12bit SAR ADC with hybrid DAC is presented, and fabricated in a standard 55-nm CMOS process. By utilizing a MUX to switch the input channel, monitoring of the temperature and voltage at critical points is achieved. Additionally, a double conversion method is also proposed for circumventing the current mismatches of the two BJT temperature sensing elements, thereby lower the circuit complexity. For temperature sensing, the sensor shows a measured inaccuracy of +/- 1.5 degrees C from-55 degrees C to 125 degrees C with an resolution of 0.86 degrees C. For voltage sensing, the ADC shows a measured DNL and INL of +0.43/-0.47LSB and +1.4/-1.1LSB, respectively. Thanks to the proposed technique, the sensor consumes low power of 182 mu W under a 1.8/1.2V supply at a conversion speed of 156kS/s, and occupies an area of 0.074mm2.

Logic gates are the fundamental components of integrated circuits (ICs). However, modern logic gates that have over one transistor encounter scaling‐down issues; most presently emerging logic gate structures with advanced materials generally could not be compatible with the foundry lines or also need more than one transistor to provide a voltage output. Here, a multifunctional multi‐terminal zero‐additional‐resistor‐process one‐transistor with the novel channel electrode design architecture (MZT) compatible with foundry lines, which alone provides a voltage output, and implement logic gates, memory, sensing and artificial synaptic behaviors, is proposed. MZT is compatible with all fabircation processes, including top‐gate processes, foundry line processes and bottom‐gate processes. It could reduce the footprint of logic NOT by 50%. It could have a memory retention time over 20 min, and its array has low half‐select disturbance. MZT exhibits artificial synaptic behaviors, with a power dissipation as low as the brain per synaptic event. MZT is proved to be fabricated by the foundry repeatedly. In the light of this, the MZT arrays demonstrate the controllable visualization recognition probability with convolutional neural networks (CNN) and faster reading speed than static random access memory (SRAM) based on simulation. MZT provides a promising strategy for many and future ICs.

The effect of the recording layer thickness (t) on the quasi-static switching characteristics in the double MgO/CoFeB interfaces perpendicular magnetic tunnel junctions with the [Co/Pt]n-based synthetic antiferromagnetic structures has been investigated. It is apparent that the switching current drops rapidly either with slightly increasing the bottom CoFeB thickness (tCoFeB ≥ 1.15 nm) or inserted Ta thickness (tTa ≥ 0.3 nm), or with marginally decreasing the upper CoFeB thickness (tCoFeB ≤ 0.75 nm), even acquiring a maximum reduction of 41.8%. The tuning mechanism of the write energy dissipation at a specific pulse width can be attributed to two parts. One is an intrinsic leverage of the effective ferromagnetic volume, spontaneous magnetization, and magnetic anisotropy field in the recording layers with a view to their dead layer. The secondary contributors may be closely related to the discrepancy between the resistance-area products of the perpendicular magnetic tunnel junction devices with the six different stack designs. Our results are instructive to the future development of practical ultralow-power chips in binary memory and logical computation fields.

The deposition of a metal oxide layer with good dielectric properties is a critical step in fabricating the gate dielectric of transistors based on two-dimensional semiconductors. However, current techniques for depositing ultrathin metal oxide layers on two-dimensional semiconductors suffer from quality issues that can compromise transistor performance. Here, we show that an ultrathin and uniform native oxide of gallium (Ga2O3) that naturally forms on the surface of liquid metals in an ambient environment can be prepared on the surface of molybdenum disulfide (MoS2) by squeeze-printing and surface-tension-driven methods. The Ga2O3 layer possesses a high dielectric constant of around 30 and equivalent oxide thickness of around 0.4 nm. Due to the good dielectric properties and van der Waals integration, MoS2 transistors with Ga2O3 gate dielectrics exhibit a subthreshold swing down to 60 mV dec-1, an on/off ratio of 108 and a gate leakage down to around 4 x 10-7 A cm-2. Ultrathin films of gallium oxide with a dielectric constant of around 30 can be formed on the surface of molybdenum disulfide using a liquid metal-based approach and used as the gate insulator in transistors.

This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion of the same input signal. First, the statistical characteristics across the channels are employed for estimating the timing mismatch; then, by comparing the output difference between the reference channel and the sub-channels that are sampled simultaneously, the deviation of the derivator can be calibrated. Finally, combining both calibration results yields an accurate final output. This proposed algorithm provides an effective solution to improve TIADC performance in high-speed data acquisition systems. The proposed architecture is applied to a 12-bit 2.4 GS/s four-channel TIADC model, and then its effectiveness is verified. The simulation results exhibit that the Effective Number Of Bits (ENOB) at an input signal frequency of 984 MHz shows a remarkable improvement from 6.88 bits to 11.92 bits. The effectiveness of this technique is also demonstrated through the off-chip calibration of a commercial 12-bit four-channel 2 GS/s TIADC using a 680 MHz input signal that is based on the actual chip results.

This paper proposed a novel all-digital blind background calibration to mitigate timing mismatch in time-interleaved analog-to-digital converter (TIADC). In estimation module, the adoption of a subtraction-based error extraction function and the design of Variable-Step-Size Least Mean Squares algorithm contribute to reducing the computational complexity and enhancing the convergence speed with optimal output accuracy respectively. In compensation module, a dual-stage Taylor series expansion structure has been introduced to effectively maintain the overall output performance. The proposed architecture is applied to a 12-bit 3 GS/s four-channel TIADC model. Its effectiveness for single-tone and multi-tone signals is proven through systematical testing and analysis. The simulation results exhibit that the Spurious Free Dynamic Range is significantly improved by 54.53 dB in the single-tone signal case, and the timing mismatch is converged after 1000 samples. The proposed calibration circuit has been synthesized utilizing a 28 nm standard cell library for assessing its hardware consumption, area (0.051 mm2) and average power dissipation (67.5 mW) within the integrated chip architecture. Our technology provides a viable optimization solution to improve efficiency of TIADC in high-speed systems.

This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and boundary effect errors. A novel approach of adding isolation devices is introduced and reinterpreted to mitigate the effect of ODM. The simulation results indicate that the inclusion of isolation devices efficiently suppresses the odd harmonics at mid-to-high frequency by a value that is 13 dB lower than before. Experimental validation is conducted on a 16-bit 250 MS/s CS-DAC fabricated in a 180 nm process.

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

Hot carrier degradation in double SOI devices was investigated under both MOSFET and BJT operation modes. It was found that hot carrier stress (HCS) induced traps deteriorate the parameters in MOSFET mode and increase the base current in BJT mode. Moreover, a recommended terminal setup between the two modes for better reliability performance is provided through further experimental results with interchanged connection. Our work contributes to the reliability analysis in SOI devices with alternative modes.

This paper presents a fully-digital background calibration method for calibrating timing mismatch in dual-channel time-interleaved analog-to-digital converter (TIADC). The proposed method estimates timing mismatch by performing correlation calculations on the outputs of sub-channels and corrects this mismatch using the improved perfect reconstruction filter bank (PRFB). The PRFB, which is improved by employing a polynomial fitting method, offers superior performance with fewer filter taps and extends the timing mismatch correction capability to almost the entire sampling clock cycle. The improved PRFB uses only one twentieth of the taps used in the original PRFB, and its dual-channel FIR filters have anti-symmetric taps. To enhance the real-time calibration capability of the system, this paper gives a fully-parallel hardware structure for calibrating offset, gain, bandwidth, and timing mismatches. The effectiveness of the proposed hardware structure is verified through a 10-bit 3GS/s dual-channel TIADC test platform. Simulation and measurement results show that the proposed calibration method significantly improves the signal-to-noise-and-distortion (SNDR) and spurious-free dynamic range (SFDR) of both single-tone and multi-tone input signals, which makes the proposed method a viable solution for practical TIADC applications.

Timing-mismatch errors among channels in time-interleaved analog-to-digital converters (TIADCs) greatly degrade the whole performance of the system. Therefore, techniques for calibrating timing mismatch are indispensable, and a new fully-digital calibration technique is presented in this article. Based on a Hilbert filter, modified moving averagers (MMAs) and inverse cosine functions, the proposed estimation algorithm is fast (within 1200 sample points) and accurate. Meanwhile, the coordinate rotational digital computer (CORDIC) algorithm, which is used to implement inverse cosine functions, is also improved, giving it higher precision. In addition, a compensation method based on second-order Taylor series approximation with less hardware resource consumption is provided. Through analyses and simulations, this calibration technique proved to be suitable for TIADCs with an arbitrary number of channels, in which the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were, respectively, improved from 24.06 dB and 24.57 dB to 67.96 dB and 85.69 dB.

This brief proposes a fully digital background estimation technique for timing mismatch in time-interleaved analog-to-digital converters (TIADCs). The improved estimation technique is a feedback method based on statistics and Taylor series expansion. Besides, an exponential moving average (EMA) with adaptive coefficient is introduced to prevent performance degradation near specific frequencies, which improves the robustness of calibration. This estimation method can maintain high performance of accuracy and convergence speed across nearly the entire input frequency band. Furthermore, it is not restricted to the number of channels, amplitude, and frequency of the input signal. The effectiveness of this technique is demonstrated through OFF-chip calibration of a commercial 12-bit four-channel 3 GS/s TIADC using a 1.01 GHz input signal. Results indicate that the proposed method converges after approximately 3000 samples, reducing spurious signals stemming from timing mismatch by 20.6, 19.3, and 18.5 dB, respectively.

This paper proposes a fully digital background calibration method for time-interleaved analog-to-digital converter (TIADC) mismatches. The method analyzes the frequency and phase of spurious signals caused by three types of mismatches in TIADCs in the frequency domain. By utilizing the Hilbert transform and frequency shifting, orthogonal basis signals located at the mismatch frequencies can be constructed. The calibration of mismatches is achieved by linearly combining the orthogonal basis signals with the estimated coefficients and subtracting them from the original signal. The estimation of coefficients is determined by evaluating the correlation between the linear combination of orthogonal basis signals and the calibrated signal. Furthermore, an exponential moving average (EMA) and least mean square (LMS) algorithm are introduced to expedite the coefficient estimation process. The entire calibration process converges in merely 600 samples, significantly improving the convergence speed. By monitoring the amplitude of the input signal and adjusting the LMS step, the algorithm is functional under different amplitude signals, enhancing the robustness. An off-chip calibration is conducted based on a commercial 14-bit, 8-channel, 2.4GSPS TIADC. Results indicate that all spurious signals are suppressed below 80 dB, and the convergence rate is consistent with the simulation.