As RF technologies continue to scale, the direct integration of airgap structures significantly narrows the back-end-of-line (BEOL) process window and introduces yield-sensitive integration challenges, resulting in severe wafer-level yield degradation. In this work, major airgap-related failure modes are identified, including abnormal airgap morphology and contact/via missing. The root causes of airgap-induced yield loss are systematically investigated, and a coordinated process-layout optimization strategy is developed, including reconfiguration of the IMD stack and enhancement of overlap margins. Wafer-level yield results demonstrate that the proposed optimization effectively suppresses airgap-related failures, stabilizing the overall yield above 99.4%. Stability and reliability of the process window are confirmed through FEM experiments.

The synergistic effects of total ionizing dose (TID) and hot carrier injection (HCI) on silicon ion-implanted and unmodified partially depleted silicon-on-insulator (PDSOI) pMOSFETs are investigated. Both the TID and HCI effects in PMOS devices involve charge trapping and the creation of interface states. The experimental results show that there is mutual promotion or inhibition between them, depending on the sequence of irradiation and HCI stress, as well as the bias condition of the HCI stress. Theoretical analysis and simulation results demonstrate that the charges in the buried oxide layer not only affect the electric field distribution within the buried oxide but also influence the front gate, further affecting the irradiation and hot carrier degradation process.

This article proposes a novel selective write-assist circuit and a Sense Amplifier (SA) with adaptive offset improvement for low-voltage Static Random Access Memory (SRAM) applications. Upon detection of a write failure in a single SRAM cell, the write-assist circuit is turned on separately to save power consumption. By adaptively improving the offset of SA, the bitline discharge time during SRAM read operations is shortened, achieving a high-speed SRAM read operation. The proposed circuit was integrated into a 256kb SRAM test chip and manufactured using a 40nm CMOS process. Measurement results show that under specific conditions, the access time is 523ps, the dynamic power is 25.03 mu W/MHz at VDD = 1.21V. The SRAM remains functional at 176MHz with a dynamic power of 11.84 mu W/MHz when VDD is reduced to 0.81V.

This paper presents an output capacitor-less LDO regulator (OCL-LDO) with high PSR and ultra-low quiescent current. The circuit utilizes a local feedback amplifier based BGR and a pseudo-dynamic biased error amplifier to improve its PSR. Hereinto, the modified super source follower solves the stability problem in the local loop and further reduces the output impedance. Furthermore, the nested miller compensation based on dynamic nulling resistor (DNR-NMC) is utilized to keep stable in the full load range. The transient enhancement circuit can reduce the overshoot and outshoot voltage by 68% and 35%, respectively. This design implemented in 180nm technology occupies an area of 0.132 mu m2 and provides a controllable output over a supply range of 2.5V-5V and the maximum output current is 100mA. The PSR is less than-75dB at 100Hz and-40dB at 10kHz with the load current of 100mA. Additionally, the line regulation and load regulation are 0.08%/V and 0.21%/A, respectively.

Flash memory, a key element in embedded systems, necessitates high voltage for its operation, which is usually provided by charge pumps. This paper presents a programmable high efficiency charge pump system in 40 nm bulk CMOS technology powered from a 1.1 V supply. The proposed system integrates low-voltage MOS self-adaptive body-biased cross-coupled charge pumps and a high-voltage MOS self-adaptive body-biased cross-coupled charge pump with a doubler structure. The system adaptively activates the appropriate charge pump combination based on the current load, working in conjunction with a novel clock coupled voltage modulation circuit to achieve reduced power consumption and improved efficiency. The programmable high efficiency charge pump system can stabilize an output voltage of 6V at 292 mu A and 8V at 235 mu A under a 50 MHz clock. It achieves a peak efficiency of 64.04% at 292 mu A current load and occupies 0.145 mm2 in area.

This paper introduces a novel low-voltage Super Junction Trench Gate MOSFET (SJ TG MOSFET) device developed from a commercial TG MOSFET product in the 12-inch technology. This SJ TG MOSFET was investigated by TCAD simulation and characterized by experiments.A novel cost-effective method was employed to form a P-type pillar (PPL) in this work, which features multiple boron implantations. It was experimentally shown that both V-B of 102.23 V and R-sp of 49.41 m Omega center dot mm(2) were achieved in this low-voltage SJ TG MOSFET device. It was distinctly demonstrated that this SJ TG MOSFET was a competitive device in some low-voltage applications.

We investigated the impact of gamma-rays and proton irradiation on the performance of high-speed modulators by exposing four-channel 4 x 100 Gbps silicon transmitter chips to both of these radiation sources. The results of our studies indicate that the modulators demonstrated exceptional radiation resistance for various combinations of energy-dose exposure to gamma-rays and proton irradiation in terms of the electro-optic modulation rate, extinction ratio, and modulation efficiency. When subjected to a cumulative radiation dose of 25 Mrad(Si) gamma-rays irradiation, the modulation bandwidth decreases from 52 to 31 GHz. Nevertheless, it was mostly restored using a 7 h annealing procedure at a temperature of 100 degrees C. Proton irradiation at different energy levels and fluences did not have significant detrimental effects on the performance of the modulators. Moreover, it did enhance the modulation efficiency at low fluence.

As embedded flash memory advances to smaller process nodes, supply voltage reductions are necessary to lower dynamic power consumption and ensure the safe operation of increasingly smaller transistors. Embedded flash memory requires reliable signal conversion across multiple voltage domains, a task typically handled by level shifters. However, achieving robust level shifter performance becomes significantly more challenging as supply voltages decrease. This paper presents a wide-range voltage, high-speed progressive level shifter utilizing a combination of 1.1-V thin-oxide and 5-V thick-oxide transistors. When combined with a charge pump, the generated intermediate voltage facilitates efficient signal conversion from low- to multiple high-voltage domains, enabling the proposed LS to achieve robust performance. Postlayout simulations in a 40-nm CMOS process demonstrate a transition delay of 1.01 ns and energy consumption of 587.86 fJ for a 0.75- to 4.5-V conversion. For a 0.75- to 9-V conversion, the delay is 1.31 ns with energy consumption of 3863.26 fJ, operating at 50 MHz with a 15-fF output load. These results underscore the robustness and efficiency of the proposed LS, positioning it as a strong candidate for embedded flash memory applications in advanced nodes with reduced supply voltages.

The integration of artificial intelligence(AI) with satellite technology is ushering in a new era of space exploration,with small satellites playing a pivotal role in advancing this field. However, the deployment of machine learning(ML)models in space faces distinct challenges, such as single event upsets(SEUs), which are triggered by space radiation and can corrupt the outputs of neural networks. To defend against this threat, we investigate laser-based fault injection techniques on 55-nm SRAM cells, aiming to explore the impact of SEUs on neural network performance. In this paper,we propose a novel solution in the form of Bin-DNCNN, a binary neural network(BNN)-based model that significantly enhances robustness to radiation-induced faults. We conduct experiments to evaluate the denoising effectiveness of different neural network architectures, comparing their resilience to weight errors before and after fault injections. Our experimental results demonstrate that binary neural networks(BNNs) exhibit superior robustness to weight errors compared to traditional deep neural networks(DNNs), making them a promising candidate for spaceborne AI applications.

A novel read circuit for embedded flash memory operating from a single 1.1-V supply is presented, featuring a negative-voltage dual-MOS transmission structure for bitline (BL) transfer and a low-voltage, high-reliability current-voltage sense amplifier (SA). This approach effectively addresses the issue of reduced read window size due to decreased BL voltage as supply voltage decreases. The proposed circuit is integrated into a 4.5-Mbit embedded flash memory test chip, fabricated using a 40-nm CMOS process. Experimental results show a read access time of 18.5 ns at a supply voltage of 0.9 V, with a read throughput of 7.78 Gbit/s and a bit density of 3.414 Mbit/mm(2).

This paper introduces a novel High-speed Ultralow power Double-Node Upsets (DNU) Tolerant Automotive Latch (HUDTAL) fabricated in the 55-nm CMOS technology. Through the integration of Muller-C-Element (MCE), Node-Hardened MCE, CLK-Gating MCE (CG-MCE), and Transmission Gate techniques, the proposed latch can fully resist DNU. Compared with similar types of latches through simulation, the proposed latch has higher critical charges and does not generate any TFs at the output that may affect the next stage circuit, saving 4.89% area power delay product on average. Additionally, it exhibits lower sensitivity to process voltage temperature variations, enabling stable operation in harsh environmental conditions.

This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, subsequently conceptualizes an ideal hardening structure for the pre-amplification stage, and proposes a radiation hardened by design (RHBD) strategy to cope with the severe single-event transient (SET) effects of high-precision voltage comparators in a space radiation environment. Analysis and verification results show that the hardening strategy exhibits excellent SET hardening performance, which can not only detect extremely small transient voltage disturbances at sensitive nodes but also effectively resist transient current pulses of various intensities generated by SETs. Compared with an unhardened high-precision comparator, the proposed one, hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques, can greatly preserve the original electrical properties and remarkably improve the tolerance of SET with little overhead. In addition, the proposed high-precision comparator significantly reduces static power consumption compared with the one hardened with the TMR technique alone and has a smaller area overhead. This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, conceptualizes an ideal hardening structure for the pre-amplification stage, and proposes a high-precision comparator hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques. This strategy not only greatly preserves the electrical characteristics but also detects extremely small transient voltage disturbances caused at sensitive nodes and effectively resists transient current pulses of various intensities, remarkably improving the comparator's tolerance to SET. image

In this paper, a novel low-cost, double-node upset (DNU) tolerant latch aiming at nourishing the lack of these devices in the state of the art was presented, especially featuring high reliability while maintaining a low-cost profile. The proposed latch is based on a low-cost single event double-node upset tolerant latch and also provides self-recoverability against double-node-upsets. The latch uses clock-controlled DICE (Dual-interlocked storage cell) cell and CE(C-Elements) cell to tolerate double-node-upsets fully. The Simulation waveforms and analysis results show that the proposed latch can maintain the correct output in any case of DNU. In addition, under the premise of high radiation tolerance, the minimum improvement of the area-power-delay product (APDP) of the proposed low-power double-node-upsets hardened latch (LPDHL) is 16.60%, compared with the latest DNU tolerant latch on the literature. In order to reduce the influence of double-node upset (DNU) on latches in single-event effects (SEE) and solve the problem of high power of the other latches, a new radiation hardened by design (RHBD), namely low-power double-node-upsets hardened latch (LPDHL) based on dual-interlocked storage cell (DICE) is proposed. image

To reduce the impact of the single-event transient (SET) effect on the high-precision comparator, based on the common high-gain pre-amplification stage structure of the comparator, a new radiation hardened by design (RHBD) method, namely, the sensitive node transient detection feedback latch (SNTDFL) technique, is proposed. The hardening technique avoids comparator erroneous output by detecting the sensitive nodes of the high-gain pre-amplification stage. The detection circuit receives the response generated by the high energy particle impacts and feeds the high level back to the sensitive nodes to latch the current comparator state. In this paper, a novel high-precision SET hardened voltage comparator based on this technique is developed. Through detailed circuit principle and simulation analysis, the functional characteristics and the hardening performance of the high-precision hardened comparator are verified. Compared with the unhardened and the TMR technique hardened comparator, the SNTDFL technique hardened comparator effectively avoids the erroneous output caused by the SET effect with less overhead and still has excellent functional characteristics.

Summary In this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications.

The performance of the Silicon Photonic Mach-Zehnder modulator (MZM) was studied under gamma-ray radiation. The experimental results showed that when the total dose of gamma-ray radiation reached up to 10 Mrad(Si), the influence on modulation efficiency of the silicon photonic MZM was negligible. However, the electro-optical(EO) bandwidth decreased by 13 % compared to that of pre-irradiation.

In this work, the effects of total dose irradiation on the parasitic bipolar junction transistor (BTJ) in 130 nm PDSOI MOSFETs were investigated. The experimental results demonstrate that irradiation-induced oxide-trap charges can modify the E-B junction barrier, and thereby make the common-emitter gain β0 of the parasitic BJT in NMOS device increase, while decreasing it in a PMOS device. Additionally, irradiation-generated oxide-trap charges in shallow trench isolation (STI) elevate the surface electrostatic potential of the gate above the STI sidewall, thus providing an additional channel from the emitter to the collector. Moreover, these charges may generate parasitic reverse conductive paths at the STI/Si interface under high dose irradiation, thereby enhancing the leakage current in the front gate channel and diminishing the significance of the parasitic BJT. Under irradiation, the electric field intensity difference between two biases leads to higher β0 of the parasitic BJT in PG-biased devices than in ON-biased ones. Furthermore, the lifting effect of irradiation on β0 increases in wide or short channel irradiated devices, which can be explained using simulations and an emitter current crowding effect model.

In this paper, a high-performance and highly-stable soft error resistant 12T (HPHS12T) SRAM cell is proposed. Based on polarity reversal design and NMOS stacked structure, the proposed HPHS12T cell can recover from any single event upsets (SEU) induced at all its sensitive nodes and even single event multiple-node-upsets (SEMNU) induced at its internal storage node pair Q-QN, while also having the maximum read static noise margin (RSNM) and write noise margin (WNM), as well as excellent write-ability. Though the HPHS12T cell exhibits a larger static hold power, it has the best overall performance of all the other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed cell a better choice for space applications.

Based on differential cascade voltage switch architecture, this paper proposes a level shifter with optimized energy consumption, constructed by stacking diode-connected NMOS and PMOS transistors and splitting input signals of the two output stages. Eventually, the overlap time of input signals of the two output stages has been reduced, during which there is a considerable short-current from high voltage source to ground. When implemented in a 110 nm CMOS process, post-layout netlist simulations show that the proposed level shifter exhibits a 2.31 ns switching delay and 819 fJ energy consumption when converting a 1.5 V input signal into 4.5 V with 10 MHz operational frequency and 15 fF output load.

Silicon photonics is considered to be an ideal solution as optical interconnect in radiation environments. Our previous study has demonstrated experimentally that radiation responses of device are related to waveguide size, and devices with thick top silicon waveguide layers are expected to be less sensitive to irradiation. Here, we design radiation-resistant arrayed waveguide gratings and Mach-Zehnder interferometers based on silicon-on-insulator with 3 µm-thick silicon optical waveguide platform. The devices are exposed to 60Co γ-ray irradiation up to 41 Mrad(Si) and 170-keV proton irradiation with total fluences from 1×1013 to 1×1016 p/cm2 to evaluate performance after irradiation. The results show that these devices can function well and have potential application in harsh radiation environments.