A half-size prototype of the multi wire drift chamber for the cooling storage ring external-target experiment (CEE) was assembled and tested in the 350 MeV/u Kr + Fe reactions at the heavy-ion research facility in Lanzhou. The prototype consists of six sense layers, where the sense wires are stretched in three directions X, U, and V; meeting 0^∘ , 30^∘ , and -30^∘ , respectively, with respect to the vertical axis. The sensitive area of the prototype is 76 cm× 76 cm . The amplified and shaped signals from the anode wires were digitized in a serial capacity array. When operating at a high voltage of 1500 V on the anode wires, the efficiency for each layer is greater than 95 301 ± 2 μm . This performance satisfies the requirements of CEE.

针对强流环境下时间投影室TPC(Time Projection Chamber)探测器高计数率、大动态范围、低功耗的读出需求，基于180 nm CMOS工艺设计了一种自动调节增益的前放芯片。该芯片由电荷灵敏前放CSA(Charge Sensitive Amplifier)、Class AB输出缓冲级、增益控制模块、触发控制模块构成。通过片内逻辑信号控制多个开关的切换，使芯片的转换增益自适应输入电荷量；并通过开关泄放，使芯片工作于1 MHz计数率。经过后仿真，在输入信号范围为2.2～16.5 pC时，积分非线性好于0.4%。该芯片已经提交foundry流片。

Advanced front-end readout chips for medium and high energy nuclear physics experiments have shown an increasing trend towards digitization in recent years,increasing system integration and reducing power consumption.Guided by critical scientific goals,the Institute of Modern Physics of the Chinese Academy of Sciences is building a central scientific installation termed as the high intensity heavy-ion accelerator facility(HIAF).HIAF fragment separator(HFRS)is an important experimental device for radioactive beam physics research on the HIAF.The characteristics of HFRS strong current and the readout demand of the large area detectors put forward the requirements of high-count rate,high integration,and high time resolution for the front-end readout electronics,and therefore the development of the advanced digital front-end readout chip is urgently needed.The paper developed a high-count rate multi-channel time measurement and serial readout circuit(HMTRC)based on 180 nm complementary metal oxide semiconductor(CMOS)process,which can accelerate the development and iteration of such digital front-end readout chips.The HMTRC has now been integrated into a self-developed 16 channel digital-analogue hybrid front-end readout chip,EDIMS,for position sensitive detectors on HFRS.When a charge signal is input,the charge-sensitive amplifier(CSA)integrates the signal into an exponentially decaying voltage signal and fans out to the time path and the energy path.In the time path,the fast shaper inputs the output signal of the CSA into the discriminator after shaping,and outputs the self-triggering signal after comparing with the threshold.The digital first input first output(FIFO)memory in each channel records information such as the timestamp and channel number corresponding to the front time of the trigger signal.In the energy path,the slow shaper integrates the output signal of the CSA into a quasi-Gaussian signal.The output signal of the peak detect and hold circuit(PDH)follows the leading edge of the output signal of the slow shaper to detect and maintain peak energy information.The analog memory based on switched-capacitor arrays stores the information.The polling readout module based on the token ring logic reads out the stored charge and time information periodically and synchronously,which has advantages in the de-sparsification and de-randomization of nuclear events and the improvement of peak count rate.The chip has been fabricated and the HMTRC has a size of 535 µm×930 μm and a power consumption of 32.31 mW.The laboratory test system consists of a chip test board,a XILINX Kintex-7 development board,a host computer,a signal generator and an oscilloscope.The field programmable gate array(FPGA)on the development board provides the master clock and control signals for the chip under test.The output data from the chip are transferred to the development board by a high-speed connector,packaged by cache processing and uploaded to the host computer via the integrated logic analyzer for analysis.The test results show that the function of the HMTRC and the coarse time of the timestamps are in line with expectations,but the fine time of timestamp between each channel is different,and there is some error compared with the theoretical value.The test results also show that the accuracy of time resolution is better than 2 ns,which is as expected,and basically meets the requirements of the application.The next version of the design will optimize the inconsistency between the channels and fine time error of the timestamp,and add the inter-integrated circuit(I2C)or the serial peripheral interface(SPI)slow control module to improve the versatility of this circuit.

HFRS (HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility (HIAF) in China. Several TPC detectors, with high count rates, are planned for particle identification and beam monitoring at HFRS. This paper presents an event-driven internal memory and synchronous readout (EDIMS) prototype ASIC chip. The aim is to provide HFRS-TPC with high-precision time and charge measurements with high count rates and a large dynamic range. The first prototype EDIMS chip integrated 16 channels and is fabricated using a 0.18- μm CMOS process. Each channel consists of a charge-sensitive amplifier, fast shaper, slow shaper, peak detect-and-hold circuit, discriminator with time-walk compensation, analog memory, and FIFO. The token ring is used for clock-synchronous readout. The chip is taped and tested.

The Multi-purpose Time Projection Chamber (TPC) for nuclear AsTrophysical and Exotic beam experiments (MATE) is being upgraded for the decay and active target experiments at the Heavy Ion Research Facility in Lanzhou (HIRFL). We have developed a gating grid driver to control the transitions between the closed and open states of the gating grid of the MATE-TPC to detect interesting rare decay events from a large amount of implanted ions. The gating grid driver is mainly composed of a digital control unit and a high-voltage switch unit. The digital control unit responds to the external trigger and generates control signals for the operation of the high-voltage control part based on the presetting instruction. The high-voltage switch unit is connected to two negative high voltages with different values and changes the voltages of neighboring wires of the gating grid based on the request for closing or opening the gate. A 500 ns switching time of the gating grid driver has been achieved from the closed to open state. The duration of the open state can be adjusted from 1 µs to 99 ms based on the experimental requirements. This gating grid driver can be used in a particle detector with a high voltage bias of up to ± 3000 V.

Three multiwire drift chamber (MWDC) detectors and readout electrical equipment had been installed in 2018 as part of the cooler storage ring external target facility (ETF) project to gather track data in the ETF. In addition to its high efficiency and adaptability, the electronic device requires high precision in terms of position and energy resolution, as well as good flexibility and efficiency of the electronics. In this article, we propose an electronic readout technique for MWDC detectors and show the implementation of a 32-channel signal processing in a single Xilinx Kintex-7 field-programmable gate array. Furthermore, we also present a thorough description of the readout firmware, with a focus on the deserialization mechanism and data processing algorithms. In addition, we conducted a series of initial tests. The results show that the proposed technique can meet the application requirement.

This paper proposes and implements a readout electronic prototype system for a Multi-Wire Drift Chamber (MWDC) detector. This system includes Front-End Electronics (FEE), Sub_Data Acquisition (Sub_DAQ), and Common Data Acquisition Unit (CDAU). Based on a self-developed Application-Specific Integrated Circuit (ASIC) chip, the FEE amplifies and reshapes the detector signals before transmitting them via a high-density micro-coaxial cable to the Sub_DAQ. The Sub_DAQ, based on a Field-Programmable Gate Array (FPGA), was designed to process MWDC signals. The Sub_DAQ can perform an analogue-to-digital conversion, online data processing, and package transmission before transmitting the data to the CDAU via a high-speed optical fibre link. The CDAU gathered data, online processed the data, and then transmitted the data to the computer via the PCIe 3.0 interface. This paper will discuss the design process, the implementation, and the initial test results of the readout electronic prototype system.

In this paper, a shaper and discriminator ASIC chip with time-walk compensation(TWC) is designed using 180 nm CMOS technology for a TPC detector which will be assembled on High energy FRagment Separator(HFRS) beamlines under construction. It comprises a fast CR-RC shaper, two comparators, and a TWC module. The peak time of the shaper is 30 ns, and the propagation delay of the comparator is 2.4 ns (25 mV Overdrive). When the dynamic range of the TPC output charge is from 10 fC to 1000 fC, the time error of the trigger signal produced by the ASIC was measured to be less than 2 ns.

基于GF 0.18 um CMOS工艺,设计并实现了ASIC芯片中的重要组成部分?阈值产生与调节电路,包括DAC模块和基于SPI慢控接口模块的控制模块.为了有效减少ASIC芯片版图面积、降低功耗,同时提高调节精度,提出通过组合高、低两个4位的DAC实现一个8位DAC的阈值调节,其中多个通道复用一个高4位DAC进行阈值粗调,每通道各自包含一个低4位DAC进行阈值细调.SPI慢控接口模块不仅实现对8位DAC输入的控制来调节触发阈值,还能够控制前放的增益和成型时间的档位.测试结果表明:DAC模块的DNL<0.10 LSB;INL<0.18 LSB;阈值粗调范围约为900 mV;阈值细调范围约为60 mV,精度误差小于7％,可满足ASIC芯片中的甄别器对阈值调节的需求.

The 12 C+ 12 C fusion reaction was studied in the range of E c.m. =8.9 to 21 MeV using the active-target Time Projection Chamber.With full information on all tracks of the reaction products,cross sections of the 12 C( 12 C,~8 Be) 16 O g.s. channel and the 12 C( 12 C,3 a) 12 C channel could be measured down to the level of a few milibarns.The 12 C( 12 C,~8 Be) 16 O g.s. reaction channel was determined to be 10 -8 +2 4 mb at E c.m. =11.1 MeV,supporting the direct a transfer reaction mechanism.The 12 C( 12 C,3α) 12 C reaction channel was studied for the first time using an exclusive measurement.Our result does not confirm the anomaly behavior reported in the previous inclusive measurement by Kolata et al.[Phys.Rev.C 21,579（1980）].Our comparisons with statistical model calculations suggest that the 3 a channel is dominated by the fusion evaporation process at E c.m. ＞ 19 MeV.The additional contribution of the 3 a channel increases the fusion reaction cross section by 10% at energies above 20 MeV.We also find that an additional reaction mechanism is needed to explain the measured cross section at E c.m. ＜15 MeV at which point the statistical model prediction vanishes.

The Multi-Wire Drift Chamber (MWDC) is among the significant detectors for CSR External Target Experiment (CEE). We require the MWDC detector’s front-end readout circuits to have a high integration, high count rate, and big dynamic range in order to measure the tracks of fore-angle products. In this paper, MWDC readout electronics verification system is shown, which is based on the front-end amplifier chip and Switched Capacitor Array (SCA) chip independently established by the project team. In the dynamic input range of 14 fC–950 fC, the readout electronics' energy measurement linearity is greater than 1%. The test results with MWDC illustrate that with a 55Fe source an energy resolution of 22.4% was acquired, and with cosmic rays the residual error is less than 400um.

该文研制了一种基于现场可编程逻辑阵列(FPGA)的自动标定装置,用于对深空粒子探测系统的自动校准和刻度.该标定装置主要包括标准脉冲产生单元、高速模数转换单元和控制与数据处理单元.其控制与数据处理单元基于FPGA实现,采用模块化的设计完成对外围电路控制及数据在线处理.通过各项实验验证,该装置可在复杂环境下实现对系统的基线稳定性、线性、能量分辨等特性的自动标定,具有高集成度、高可靠性、高自动化程度和灵活配置等特点,为深空探测器飞行中的在板标定和自动测试提供手段.

为提高前端读出电路集成度,并验证自主研发的主放大器专用集成电路芯片MCSA于在束PET成像系统中的应用可行性,采用MCSA替代商用器件,设计了一款新型在束PET前端读出电路.该电路由能量链、时间链、数据采集与处理单元组成.测试结果表明:电路的线性度优于0.78％,全范围平均噪声小于1 mV,时间分辨为341.5 ps,在1～10 kHz范围不同频率输入信号下工作稳定,能量分辨率为5.2％,二维位置谱中各像素点清晰且位置易分割.主要性能指标达到或接近采用商用芯片作为主放的前端读出电路,可满足应用需求.

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and 22Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

为实现重离子治癌装置中γ-γ符合时间的高精度和高分辨率测量,设计实现了符合时间的测量系统,该系统主要由高速比较器构成的定时甄别电路和基于现场可编程逻辑阵列(FPGA)的时间-数字转换(TDC)电路构成.FPGA-TDC通过"粗"时间和"细"时间结合的方法实现精确的时间测量:"粗"时间测量采用二进制计数器实现,"细"时间测量基于片内缓冲器和寄存器阵列构成的级联延迟链实现.实测结果表明,该符合时间测量系统的本征时间间隔测量分辨好于276 ps(FWHM).构建了H8500耦合LYSO晶体阵列组成的测量系统,并对22Na 511 keVγ射线进行测试,结果表明时间测量精度优于1.12 ns(FWHM),且通过统计分析有效符合时间得到的晶体阵列位置映射散点图清晰.

研制一套可用于高计数率气体探测器的读出电子学原型机系统,包括前端板、数据采集板和上位机.前端板采用一款先进的前端读出专用集成电路(ASIC)芯片实现对探测器信号的测量和模数转换;数据采集板利用现场可编程门阵列(FPGA)实现对数据的分析、处理和传输;上位机实现控制指令发送、PC端数据接收及存储等.在2.2～99 fC的输入范围内,原型机各通道积分非线性均好于0.24％;联合探测器使用55 Fe放射源测试,结果好于相同条件下的商用电子学.可满足20 kHz计数率下GEM-TPC探测器的读出需求.

发生在中子星壳层内的丰中子熔合反应对中子星演化以及X射线超级爆等现象均会产生影响.受限于放射性束流强度和反应机制的复杂性,实验数据极其缺乏,难以有效约束理论模型.基于活性靶技术的时间投影室(Time Projection Chamber,TPC)将工作气体作为反应靶,具备近4π立体角接受度和三维径迹重建能力,能够实现对反应事件的全记录,显著提高了探测效率,大幅降低了熔合反应截面测量对束流强度的要求.我们研制了240路信号读出的TPC,并使用放射性束流16N对探测器进行了测试,探索了该实验方法的可行性和有效性.为了得到更加精确的反应产物径迹,对反应事件做出更好的筛选,进一步发展了1024路信号读出TPC,并开展了12C+12C库仑位垒附近熔合反应截面测量实验,初步实验结果与已有实验数据符合较好.

为了实现重离子治癌in-beam PET系统中能量信号的高精度测量,该文设计并实现了一款多通道滤波成形专用集成电路(ASIC)芯片.该芯片包含4个通道,每通道由极零相消、低通滤波以及增益补偿缓冲输出电路组成,特点为:基于3.3 V供电;采用350 nm CMOS工艺设计;流片尺寸为2.6 mm×1.25 mm.实验室电子学性能测试表明:该芯片具有4挡可调达峰时间(50 ns、100 ns、1 us、2 us),动态范围可达?0.8～+1.0 V,每通道功耗为6.6 mW,线性度优于0.12％,能量分辨优于0.3％,长时间工作稳定,通道串扰低于0.32％,增益误差小于1.01％.经放射源22Na与LaBr3探头和光电倍增管(PMT)联合测试表明,该芯片能量分辨优于商用ORTEC 572主放插件,能够实现高精度的in-beam PET能量信号测量.

为满足硅微条探测器研制的需求,本文研制了一款多通道低噪声电荷灵敏前放ASIC芯片.设计完成电荷灵敏前置放大电路和极零相消电路;并分析电路的积分非线性、噪声斜率、可靠性等指标参数.该电荷灵敏前放输入动态范围20～830 fC时,等效输入噪声为685.73+32.37 e-rms/pF.

In this paper, a four-channel Application Special Integrated Circuit (ASIC) chip based on 0.18 μm CMOS technology is developed for the high speed real-time measurement of the particle position information. Each channel in the chip includes a Polar-zero cancellation circuit, a low-pass filter, a discriminator and a pulse shaping circuit. The linearity of the filter,the shaping time and the reliability of circuit are also described in detail.