Spiking Neural Networks pose their superiority over any existing Artificial Neural Networks in terms of power and their property of leaning more towards imitating biology while solving cognitive tasks. Conventional spiking neurons react to unipolar input signals only, which makes it inconvenient for bipolar signal processing. Recently, a modified variant of the Silicon Spiking Neuron, known as the Bidirectional Spiking Neuron (BSN), has been proposed to address the limitations of existing silicon neurons. A prototype of the BSN has been implemented in TSMC 65nm technology node. The design takes a silicon area of 52 & micro;m & times; 72 & micro;m. The prototype has been extensively characterized, and the corresponding results are reported in this research. The BSN hardware is capable of sensing a wide range of bipolar input currents from-8 & micro;A to +8 & micro;A and producing spikes with a maximum frequency of 3 MHz. Additionally, an SNDR of 20 dB is feasible when using the design as a pulse density modulator. The bipolar signal sensing and spiking response pave the way to find the proposed design's applications in signal processing and cognitive tasks.
In this work, a high-linearity 8-phase CMOS-targeted-calibration phase interpolator (PI) is proposed. In classical current-mode logic (CML) PIs, improvement efforts primarily focus on correcting the CML signal phase error, while neglecting a significant transfer phase error that occurs when converting the CML signal to the CMOS signal, resulting from the amplitude differences of CML phases and the threshold variation of the transfer circuit. To address this problem, a CMOS-signal-targeted calibration technique is proposed, which considers both error sources: the CML inherent phase error and the transfer error from CML to CMOS. The phase error will be extracted directly from the final CMOS signal, and the calibration will be implemented according to this total phase error. In the proposed calibration scheme, the specific CMOS phases (22.5 degrees phase group) are adopted as phase references, which have identical CML amplitudes before CMOS to avoid the transfer error; and other CMOS phases will be calibrated based on the references. Fabricated in a 65nm CMOS process, the chip achieves an integral non-linearity (INL) of less than 2.53 LSB and a differential non-linearity (DNL) of less than 0.77 LSB with 9 bits resolution across a frequency range of 3 to 7.5 GHz.
This brief presents a 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-linearity data acquisition modules in precision industrial process control, employing a redundant split capacitor array. To mitigate the parasitic capacitance effects around the bridge capacitor, an improved floating-node calibration scheme (FNCS) is proposed, which incorporates an auxiliary calibration capacitor array to align the effective weights of the least significant bit (LSB) sub-array with their ideal values. Fabricated in a 180 nm BCD process, measurement results demonstrate that the proposed calibration scheme improves the spurious-free dynamic range (SFDR) from 75.76 dB to 94.92 dB and the signal-to-noise-and-distortion ratio (SNDR) from 69.07 dB to 80.33 dB, while enhancing converter linearity by reducing the differential nonlinearity (DNL) from -1/+ 1.72 LSB to -0.79/+ 1.01 LSB and the integral nonlinearity (INL) from -7.10/+ 6.85 LSB to -1.89/+ 1.84 LSB.
This brief presents an ultra-compact Doherty PA based on the three-coil-coupling-network (TCCN). The TCCN supports load modulation while satisfying impedance matching, and imposes minimal constraints on the output parasitic capacitance of the transistors. Moreover, a detailed parametric analysis is conducted, clarifying the relationship between the traditional 90 degrees equivalent lumped matching network and the specific parameters of the TCCN. A Ka-band Doherty PA prototype is fabricated in 65nm CMOS process to validate the effectiveness of this method, with a total core area of 0.074 mm(2). At 27GHz, the proposed DPA achieves a peak power output of 21.9 dBm, a peak power-added efficiency of 27.8%, a power-added efficiency at 6dB power back-off of 18.76%, with a maximum power density of 2.09 W/mm(2).
A single-ended transmitter (TX) employing a charge-pump-aided main and sub pre-emphasis feed-forward equalizer (FFE) for low-power memory interfaces is presented. By overcoming the voltage headroom limitation of V-SS termination, the proposed scheme increases the voltage swing while compensating for channel loss. To mitigate FFE degradation at high data rates and under severe channel loss, an additional on-demand sub pull-up FFE driver and sub pull-down charge pump are introduced. These selectively enhance equalization during bit-toggling patterns and at transitions after consecutive identical digits, improving signal integrity compared with conventional designs. Fabricated in a 28-nm CMOS process, the TX occupies an active area of 0.0065 mm(2) and achieves 18-Gb/s single-ended signal transmission over a channel with a -15.7 dB loss. The measured power consumption is 18.85 mW, corresponding to 1.05 pJ/bit and a figure of merit of 0.067 pJ/bit/dB.
This brief presents a compact sinusoidal current generator (SCG) for bio-impedance (Bio-Z) measurement. Tominimize overall circuit overhead and power consumption, the SCG is implemented with only a 2-bit/128-sample triangle Sigma-modulatedlook-up table (triangle Sigma M-LUT), a 2-bit resistive digital-to-analog converter (RDAC), a Gm-C filter and a transconductance (TC)stage followed by an output stage. The original 2-bit data stream is generated by an off-chip behavioral model for a 2-bitdigital MASH 1-1 triangle Sigma modulator (triangle Sigma M) with a 12-bit/128-samplesinusoidal LUT as its input. Then, a hybrid particle-swarm-simulated-annealing (PSO-SA) algorithm is employed to select an optimum 2-bit/128-sample sequence that ensures the highest linearity for the on-chip LUT of the SCG. Fabricated in a180-nm CMOS process, the chip occupies 0.154 mm(2) and consumes 112.9 mu W under 1.8 V for a typical output current of 20 mu A(pp )at 20 kHz, achieving a total harmonic distortion upto the 20thharmonic (THD20) of 0.0809% and a SFDR of 64.4 dB. Compared to prior similar types of designs, this work achieves area reduction up to 50%, making it suitable for wearable and implantable biomedical devices
Artificial Intelligence (AI) processors and Digital Signal Processing (DSP) chips require high-efficiency arithmetic units, while glitch-induced power has become a major obstacle to further efficiency improvement. To address this, a hybrid-polarity logic design method and an automated algorithm are proposed for low-power and glitch-optimized arithmetic units. The output inverters of full/half adders are removed to eliminate redundant switching and alleviate path imbalance. The logical duality of these inverted cells is exploited to enable both conventional logic (positive polarity) and its inverted form (negative polarity) to coexist and hybrid-propagate in arithmetic units. Then, a glitch-analysis-based inverter re-insertion strategy is used to ensure logic correctness with minimal power cost. The automated algorithm merges partial products from complex computations and explores hybrid-polarity circuit netlists with optimized power efficiency. Simulated in a 28 nm CMOS process, the proposed unsigned and signed multipliers achieve up to 54.40% and 55.92% power gains, 13.67% and 11.43% delay reduction, respectively, compared with their corresponding Design Compiler-generated baselines. When applied to dot-product modules in an AI accelerator, our design achieves up to 57.87% power reduction. The results verify the effectiveness of our hybrid-polarity design in mitigating glitches and enhancing efficiency for large-scale digital systems.
This brief presents PredLM, a hardware-algorithm co-designed accelerator that aggressively reduces external memory access (EMA) to achieve real-time large language model (LLM) decoding. First, we introduce a simple but effective Key-Value (KV) cache management policy so that the size of KV cache is fixed regardless of the context length, significantly reducing the EMA for the KV cache. Second, we propose a dynamic zero-activation prediction scheme for feed-forward networks, allowing the hardware to dynamically skip unnecessary multiply-accumulate operations and weight fetches. To seamlessly support these predictive algorithms, PredLM features a homogeneous processing element array able to support the execution of both structural sparse and dense vector-matrix multiplications. Implemented in a 28-nm CMOS technology and evaluated with the OPT-1.3B and Llama2-7B models, PredLM achieves a time-per-output-token of 1.76 and 9.41 ms/token and an energy efficiency of 19.77 and 105.09 mJ/token with negligible perplexity degradation, delivering up to $18.1 imes $ higher throughput and $4.92 imes $ better energy efficiency compared to state-of-the-art LLM accelerators.
This brief addresses phase locking and frequency synchronization in undirected networks of second-order Kuramoto oscillators with bounded intrinsic-frequency heterogeneity. Existing fixed-time designs for oscillator networks often rely on nonsmooth feedback and rarely quantify how regulation effort is distributed across nodes. We propose a smooth fully distributed controller that reinforces coupling and applies a two-regime fixed-time injection with hyperbolic-tangent smoothing, enabling practical fixed-time convergence without discontinuous switching. A sharp pseudoinverse-based tuning condition is derived to guarantee entry into and invariance of a phase-cohesive region, which yields uniform sector bounds for the sinusoidal coupling along the closed-loop trajectory. Within this cohesive regime, we establish a uniform practical fixed-time settling-time bound independent of initial conditions and characterize the tunable residual accuracy induced by smoothing and heterogeneity. We further derive an explicit tunable upper bound on the disparity of accumulated control energy across nodes, linking fast synchronization to balanced actuation burden. Numerical examples demonstrate multi-trajectory synchronization, cohesiveness preservation, and the resulting energy-disparity behavior.
This brief presents a high-precision, low-temperature-drift on-chip temperature sensor-based current reference (OCTS-CR) for loop-powered 4-20 mA transmitters. The architecture innovatively leverages an integrated on-chip temperature sensor to achieve a profound synergy between realtime thermal data and the "time-for-precision" design strategy. By mapping resistance characteristics from the spatial domain into the time domain, the system utilizes temperature sensor monitoring data to drive a 16-bit Sigma-Delta DAC to generate pulse density modulation (PDM) signals. This enables quasi-continuous adjustment of equivalent resistance, which effectively neutralizes temperature fluctuations while circumventing the parasitic effects and area constraints inherent in traditional resistor arrays. Additionally, a robust dual-stage calibration mechanism combining offline parameter pre-loading with sensor-based online digital compensation is implemented to enhance compensation resolution. Fabricated in a 0.18 mu m CMOS process with a core area of 0.144 mm(2), experimental results from-40 degrees C to +125 degrees C demonstrate that the 200 mu A primary current yields an average temperature coefficient (TC) of 3.5 ppm/degrees C with a relative standard deviation (RSD) under 0.05%, achieving a state-of-the-art precision level. Simultaneously, the system provides a proportional replica current source of 32 mu A featuring a TC of 29.3 ppm/degrees C and an RSD below 0.3% for versatile application requirements.
Infrared and visible multimodal images play a critical role in autonomous driving and robot navigation. Image registration, as a prerequisite step, directly affects the performance of the subsequent high-level vision tasks. Due to the inherent differences in imaging mechanisms, the infrared images often exhibit complex non-rigid displacements relative to visible images, which makes the precise alignment challenging. To address this issue, a multimodal image registration method based on multi-scale stationary velocity fields is proposed. Firstly, a Coordinate Attention Fusion module (CAF) and a Stationary Velocity Field Deformation Prediction module (SVFDP) are designed to integrate multi-scale features and iteratively refine the deformation field for accurate registration. Secondly, a bidirectional registration framework is employed during training, leveraging the symmetric modality similarity loss to reduce imaging discrepancies between modalities. Finally, the comprehensive experiments on the RoadScene dataset show that the proposed method outperforms existing approaches in MSE, NCC, and PSNR, achieving 0.00212, 0.9786, and 27.33 in low-deformation scenarios, and maintaining superior performance under high deformation, which demonstrates the method’s superiority in cross-modal registration.
This brief presents a high-linearity discrete-time (DT) Zoom analog-to-digital converter (ADC). To enhance linearity and simplify implementation, a coarse first-order sigma-delta modulator (SDM) followed by a 16-tap finite-impulse-response (FIR) DAC is employed, inherently suppressing harmonic distortion and eliminating the complex hardware associated with a conventional successive-approximation register (SAR) ADC and dynamic element matching (DWA). The proposed architecture achieves a 35 dB improvement in third-harmonic distortion (HD3) over a conventional 4-bit SAR-based implementation. Fabricated in a 180-nm CMOS process, the prototype measures a 106-dB signal-to-noise-and-distortion ratio (SNDR), a 109.7-dB dynamic range (DR), and a 111.1-dB spurious-free dynamic range (SFDR) over a 1-kHz bandwidth, while consuming $63.1\mu $ W from a 1.8-V supply at an 800-kHz sampling rate. This corresponds to a Schreier figure-of-merit (FoM) of 178 dB based on SNDR and 181.7 dB based on DR, without employing DWA techniques.
This brief proposes a dual-parasitic-aware second-harmonic (2f(0)) control method for continuous Class-J power amplifier (PA). To systematically investigate the effects of device parasitics, this work jointly considers the C-gs-induced current-shaping effect and the C-ds-induced impedance migration. Based on this analysis, the passive-realizable second-harmonic impedance region at the C-ds de-embedding plane is first derived while accounting for the effect of C(g)s . The associated efficiency trend is also obtained, thereby establishing an accurate second-harmonic impedance control method for practical matching-network design. To validate the proposed method, a continuous Class-J GaN MMIC PA is designed and fabricated in a 0.25 & micro;m GaN-on-Si process. The measured results show a drain efficiency of 59.2%-63.3% and a saturated output power of 36.9-37.6 dBm over 2.1-2.9 GHz.
Magnetic suspension balances (MSB) require filters with extremely low cutoff frequencies to enhances the readability of the mass indicator, which inevitably introduces significant response delays. To address this issue, a dynamic dual-channel adaptive filtering method is proposed in this brief. The fusion ratio of the slow and fast channels is indirectly supervised by the real-time levitation error, enabling adaptive integration of their respective characteristics. As a result, the proposed method preserves the noise suppression capability of the slow channel while fully exploiting the dynamic response of the fast channel without amplifying sensor noise. Experimental results obtained on a novel three-axis MSB demonstrate that this method achieves an 87.2% improvement in response speed at the cost of only 7.95% steady-state accuracy. For continuous measurements like MSB, which inherently possess high precision, this represents a significant enhancement in responsiveness.
This article presents a second-order core-injection sub-ranging voltage reference with an ultra-low temperature coefficient (TC) over a wide temperature range for Internet-of-Things (IoT) applications. Based on a shunt-PTAT second-order temperature-compensated voltage reference, a resistor-ratio based core-injection sub-ranging is applied in the voltage reference for lower TC. The proposed voltage reference was designed and fabricated in a standard 65-nm CMOS technology. The proposed second-order core-injection sub-ranging voltage reference achieves an average TC of 0.95 ppm/degrees C (sigma =0.16 ppm/degrees C) after trimming from - 60 degrees C to 85 degrees C, and the worst-case TC is 1.17 ppm/degrees C. It consumes 29 mu A at 27 degrees C and occupies 0.09 mm(2).
To enhance the control performance of surface-mount permanent magnet synchronous motor (SPMSM) under low switching-to-fundamental frequency ratios (SFRs), an improved discrete-time current regulator (IDCR) is proposed in this brief. The regulator naturally aligns with digital implementation, effectively avoiding performance degradation due to discretization. The designed feedback controller allows arbitrary placement of system poles and eliminates speed-dependent phase terms, ensuring a constant critically damped characteristic. Furthermore, the IDCR achieves precise orthogonal decoupling and, separately, does not require complex predictive computation. The proposed method significantly improves current control performance under low SFRs conditions, and experimental results further verify its effectiveness and superiority.
Poor angular resolution is a major problem in modern radar systems. The multiple input and multiple output (MIMO) radar uses N transmitters and N receivers to equivalently form N-2 virtual elements to expand the aperture. However, this level of virtual array expansion is not enough to further improve the angular resolution and reduce the number of transceiver elements. In this work, we use an additional dimension to further expand the virtual array. By stimulating the array with k different frequencies, we can expand the virtual elements to N-2k in addition to MIMO operation. The simulation results show that with 4 transmitters and 4 receivers, we can achieve 0.35 degrees angular resolution when exciting the array with 1-GHz and 4-GHz signals. Furthermore, we set up a proof-of-concept frequency-modulated continuous-wave (FMCW) radar experiment with 1 transmitter and 4 receivers to achieve 12.3 degrees angular resolution. Our proposed virtual array expansion technique can significantly reduce the number of transceivers and antenna elements in MIMO radars and improve angular resolution.
This brief presents a ring-VCO-based type-II double-sampling phase-locked loop (DSPLL) by jointly engineering bandwidth extension and reference spur suppression. Loop bandwidth is extended by inserting a unit-gain buffer (UGB) between the sampling and holding capacitors, introducing a source-degeneration zero in the G(M), and placing another UGB between the loop filter and ring VCO to compensate the phase margin, thereby suppressing ring VCO phase noise. Low reference spur is achieved adopting a T-shape switch for sampling, an F-shape switch for holding, and a narrow-pulse timing scheme with a shared holding clock, which mitigates the voltage ripple induced by the sampling and holding nonidealities. Fabricated in 65-nm CMOS, the proposed DSPLL achieves an RMS jitter of 119-fs integrated from 1-kHz to 100-MHz, a reference spur level of -88.2-dBc with a jitter-power figure-of-merit of -244.1-dB.
In this article, a 0.1-1.2 GHz broadband balun low-noise amplifier (LNA) achieving low-power operation and balanced output loads using a current-reuse-enhanced local-feedback architecture is presented. The proposed topology employs a current-reuse inverter-based common-source (CS) stage to increase the effective transconductance without additional DC current, thereby strengthening the loop gain of the local-feedback common-gate (CG) stage and relaxing the intrinsic CG g(m) requirement for wideband input matching. As a result, an improved gain-noise-power trade-off is achieved while maintaining balanced differential output. Fabricated in a 65-nm CMOS process, the proposed balun-LNA achieves a minimum noise figure of 2.35 dB, a maximum voltage gain of 28.9 dB, and S-11 < -10 dB over a 1.2 GHz bandwidth. The measured peak IIP3 and OIP3 are -5.6 dBm and 23.3 dBm, respectively. The LNA consumes 3.2 mA from a 1 V supply and occupies an active area of 0.027 mm(2).
This brief presents a PAM-4 sliding-block decision feedback equalizer (SB-DFE) employing the correction under uncertainty with reverse-decision evaluation (CURE) scheme. Conventional SB-DFE resolves timing bottlenecks in high-tap DFE by breaking the feedback loop, but remains vulnerable to intra-block error propagation. To address this, the CURE scheme is integrated for localized sequence estimation, which conditionally evaluates candidate sequences prompted by unreliable decisions to suppress error propagation with minimal complexity. Leveraging the SB-DFE structure to compensate for long-tail post-cursor intersymbol interference enables the use of a shortened feed-forward equalizer (FFE). This provides a higher signal-to-noise ratio for CURE than 4-state maximum likelihood sequence detection (MLSD), as the latter suffers from noise amplification in its longer FFE. Field-programmable gate array-based link emulation confirms the proposed architecture outperforms 4-state MLSD across various noise conditions. ASIC synthesis in a 28-nm FD-SOI technology further confirms that the design reduces area and power by $2.90 imes $ and $4.05 imes $ , respectively, relative to the MLSD benchmark.
