The intrinsic FinFET device structure can provide an estimated 10-20% reduction in delay relative to planar FETs at the 22 nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45 nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Omega-um.

We demonstrate, for the first time, modulation of power-performance of a ring oscillator fabricated on thin-BOX (buried oxide) FD (fully-depleted) SOI using independent backgate controls for nFET and pFET. The thin BOX facilitates an effective modulation of ring characteristics with small (1-2V) independent backgate voltages. Leakage current per stage can be reduced by more than 100times with 30% increase of inverter delay. In addition, the inverter delay can be improved by 15% with 2times increase of the stand-by current. Compatible with conventional CMOS process, our results suggest the backgate technology, an additional knob for power/performance optimization and variability control, is attractive for continued CMOS scaling.

In this letter, we show that undoped-body extremely thin SOI (ETSOI) MOSFETs with SOI thickness in the 4-6-nm range have excellent short-channel control down to 20-25-nm gate lengths, suitable for the 22-nm technology node and beyond. We demonstrate that 6-nm-thin ETSOI devices can deliver high drive currents required for logic applications. Finally, we bring to fore the need for improvements in etch and doping processes to reduce series resistance of 4-nm-thin ETSOI devices in order to make them a viable option for the 15-nm technology node.

The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.