Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories.

For the lognormal distribution, an unbiased estimator of the squared coefficient of variation is derived from the relative ratio of sample arithmetic to harmonic means. Analytical proofs and simulation results are presented.

A switched-capacitor DC-DC voltage converter in 45nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm(2) for 2V-to-0.95V conversion at 100MHz. Operation in step-up and step-down modes is demonstrated. Combined with stacked voltage domains, self-regulation capability enables further efficiency improvement.

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8× improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs.