This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V/sub T/ and off-current I/sub 0FF/ using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V/sub T/ and I/sub 0FF/ due to hysteretic floating-body charge are quantified for devices in L/sub eff/=0.2- and 0.1-/spl mu/m design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-/spl mu/m design space.

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V/sub DD/. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior.

Hysteretic time-transient floating-body effects are of great concern in designing partially-depleted (PD) SOI circuits. It has been demonstrated that these hysteretic floating-body effects can give rise to irregular signal propagation such as frequency dependent propagation and pulse stretching. However, these floating-body effects are known to offer enhancement of current drive over an equivalent SOI body-contacted device. Thus, it may be desirable to keep the body floating so long as the hysteretic effects can be minimized by proper device design. In order to evaluate a device design for hysteresis effect, a methodology is required which can bound the severity of hysteretic effects. In this work, a simulation method using MEDICI to evaluate PD-SOI MOSFET hysteresis effects is introduced and applied to several device designs. Two designs which eliminate hysteretic floating-body effects in PD-SOI CMOS inverters are demonstrated

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and V/sub DD/ for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem.

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L(eff) = 0.2 mu m is examined as a function of drain bias, gate pulses of varying magnitude (V-GS), pulse duration, and pulse frequency, At fixed V-DS, the gate is pulsed to values ranging from 0.1 V above V-T to V-GS = V-DS. A slow transient is seen when the drain is biased at a V-DS where the current kink is observable, This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate, For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding de, and that the kink characteristic of PD MOSFET's disappears, However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies, No transient current effects were observed in fully-depleted SOI MOSFET's.

Excess collector current in irradiated NPN BJTs is linked to an oxide-trapped-charge-induced inversion layer acting as an additional emitter. Excess collector current is modeled by interpreting the inversion layer as an extension of the emitter.

A physically based comparison between hot-carrier and ionizing radiation stress in BJT's is presented, Although both types of stress lead to qualitatively similar changes in the current gain of the device, the physical mechanisms responsible for the degradation are quite different, In the case of hot-carrier stress the damage is localized near the emitter-base junction, which causes the excess base current to have an ideality factor of two, For ionizing radiation stress, the damage occurs along all oxide-silicon interfaces, which causes the excess base current to have an ideality factor between one and two for low total doses of ionizing radiation, but an ideality factor of two for large total doses, The different physical mechanisms that apply for each type of stress imply that improvement in resistance to one type of stress does not necessarily imply improvement in resistance to the other type of stress, Based on the physical model, implications for correlating and comparing hot-carrier-induced and ionizing-radiation-induced damage are discussed.

The excess base current in an irradiated BJT increases superlinearly with total dose at low-total-dose levels. In this regime, the excess base current depends on the particular charge-trapping properties of the oxide that covers the emitter-base junction. The device response is dose-rate-, irradiation-bias-, and technology-dependent in this regime. However, once a critical amount of charge has accumulated in the oxide, the excess base current saturates at a value that is independent of how the charge accumulated. This saturated excess base current depends on the device layout, bulk lifetime in the base region, and the measurement bias. In addition to providing important insight into the physics of bipolar-transistor total-dose response, these results have significant circuit-level implications. For example, in some circuits, the transistor gain that corresponds to the saturated excess base current is sufficient to allow reliable circuit operation. For cases in which the saturated value of current gain is acceptable, and where other circuit elements permit such over-testing, this can greatly simplify hardness assurance for space applications.

We have performed capacitance-voltage (C-V) and thermally-stimulated-current (TSC) measurements on non-radiation-hard MOS capacitors simulating screen oxides of modern bipolar technologies. For 0-V irradiation at similar to 25 degrees C, the net trapped-positive-charge density (N-ox) inferred from midgap C-V shifts is similar to 25-40% greater for low-dose-rate (< 10 rad(SiO2)/s) than for high-dose-rate (> 100 rad(SiO2)/s) exposure. Device modeling shows that such a difference in screen-oxide N-ox is enough to account for the enhanced low-rate gain degradation often observed in bipolar devices, due to the similar to exp (N-ox(2)) dependence of the excess base current. At the higher rates, TSC measurements reveal a similar to 10% decrease in trapped-hole density over low rates. Also, at high rates, up to similar to 2.5-times as many trapped holes are compensated by electrons in border traps than at low rates for these devices and irradiation conditions. Both the reduction in trapped-hole density and increased charge compensation reduce the high-rate midgap shift. A physical model is developed which suggests that both effects are caused by time-dependent space charge in the bulk of these soft oxides associated with slowly transporting and/or metastably trapped holes (e. g., in E(delta)' centers). On the basis of this model, bipolar transistors and screen-oxide capacitors were irradiated at 60 degrees C at 200 rad(SiO2)/s in a successful effort to match low-rate damage. These surprising results provide insight into enhanced low-rate bipolar gain degradation and suggest potentially promising new approaches to bipolar and BICMOS hardness assurance for space applications.

Analysis of radiation damage in modern NPN bipolar transistors at various dose rates is performed with a recently introduced charge separation method and pisces simulations. The charge separation method is verified with measurements on metal-oxide-semiconductor capacitors. Gain degradation is more pronounced at lower dose rates. The charge separation technique reveals that depletion-region spreading and effective recombination velocity are both greater for devices irradiated at lower dose rates.

The design issues associated with termination structures for low-voltage (200 V class), vertical, integrated power devices are described and contrasted with common design guidelines for high-voltage devices. A comparison of single field phase, two-level field plate, field ring, and field plate/field ring methods is presented. Performance criteria are breakdown voltage, manufacturability, oxide charge sensitivity, and area consumption. The combination field plate/field ring method is superior to the other methods unless extremely low area consumption is required. Extensive device simulations as well as experimental data confirm these conclusions.

Process and device simulation software tools are used to produce an animated visualization of the mechanisms involved in the ionizing-radiation and hot-carrier stress responses of BJTs. A physically-based model is presented, which compares ionizing-radiation response with hot-carrier response in poly-silicon-emitter BJTs. During ionizing radiation, positive charge accumulates along the oxide-silicon interface. The accumulated charge causes excess base current to flow, characterized by an ideality factor between one and two for low total doses of ionizing radiation, and an ideality factor of two for high total doses of ionizing radiation. During hot-carrier stress, the oxide damage is localized near the emitter-base junction, and the excess base current has an ideality factor of two.<>

It is shown experimentally and through simulation that reduced screen oxide thickness leads to increased breakdown voltage of the emitter-base junction (BVebo) and reduced peak electric field at breakdown, which translates into improved hot-carrier reliability. The effect of reduced screen oxide thickness on the peak cutoff frequency is minimal. For these devices, thinning the screen oxide from 55 to 35 nm increases BVebo by 0.2 V, improves the hot-carrier-induced excess base current by more than an order of magnitude at a base-emitter voltage of 0.6 V, and degrades the peak cutoff frequency by only 3 percent

The effects of the midgap-level interface trap density and net oxide charge on the total-dose gain degradation of a bipolar transistor are separately identified. The superlinear dose dependence of the excess base current is explained.

The role of net positive oxide trapped charge and surface recombination velocity on excess base current in bipolar junction transistors (BJTs) is identified. The effects of the two types of damage can be detected by plotting the excess base current versus base-emitter voltage. Differences and similarities between ionizing-radiation-induced and hot electron-induced degradation are discussed.

The issues associated with termination structure design for vertical, integrated power devices are defined. The interaction of the oxide thickness running over the device isolation and the breakdown voltage of the device is explored. In light of these constraints, a comparison of single field plate, two-level field plate, field ring only, and combination field plate/field ring termination structures is performed. Combination field plate/field ring structures are seen to provide significantly higher breakdown voltage than other structures while consuming little additional area. The simple fabrication and design constraints for combination field plate/field ring termination structures makes them attractive options for integrated as well as discrete power devices