Hardened-by-design (HBD) SRAMs are shown to be latchup immune in four commercial foundry technologies. The single-event error rates are shown to be less than 10-9 errors/bit/day for these HBD SRAMs. We also report total-dose and prompt-dose hardness results. Hardness assurance of HBD SRAMs in commercial processes is considered

The total-dose response of gated lateral PNP transistors is presented for the first time for the various enhanced low-dose-rate sensitivity (ELDRS)-related test conditions of Mil-STD 883F Test Method 1019.6. We compare the PNP results to those of NPN transistors from ELDRS test chips manufactured at National Semiconductor Corporation (NSC). These data provide a physical basis for the limitations placed on the TM1019.6 ELDRS tests and confirm the conservative nature of these tests for the NSC ELDRS process.

We present data showing a new total-dose-induced parasitic effect in enclosed-geometry transistors. A model for this new effect shows that the normal radiation-induced edge leakage current becomes gate controlled in ringed-source transistors. Small width-to-length (W/L) N-channel field-effect transistors (NFETs), often used in analog designs, show an additional drain current and transconductance, because the gate-controlled leakage current approaches the magnitude of the ideal channel current.

The high and low dose rate responses of bipolar transistors in a bipolar linear circuit process technology have been studied with specially designed gated lateral pnp test transistors that allow for the extraction of the oxide trapped charge (N/sub ot/) and interface trap (N/sub it/) densities. The buildup of N/sub ot/ and N/sub it/ with total dose is investigated as a function of the irradiation gate voltage at 39 rad/s and 20 mrad/s for three variations of the final passivation layer (all variations had the same oxide covering the active region of the devices). The three variations in final passivation were selected to exhibit minimal degradation at high and low dose rate (no passivation), significant degradation at high and low dose rate (p-glass/nitride) and enhanced low dose rate sensitivity (ELDRS) (p-glass only). It is shown that the increase in base current is dominated by increased N/sub it/ and the "true" low dose rate enhancement in the ELDRS parts occurs for zero and negative gate voltage, but is eliminated for large positive gate voltage and elevated temperature irradiation. Implications for ELDRS models are discussed.

We have performed capacitance-voltage (C-V) and thermally-stimulated-current (TSC) measurements on non-radiation-hard MOS capacitors simulating screen oxides of modern bipolar technologies. For 0-V irradiation at similar to 25 degrees C, the net trapped-positive-charge density (N-ox) inferred from midgap C-V shifts is similar to 25-40% greater for low-dose-rate (< 10 rad(SiO2)/s) than for high-dose-rate (> 100 rad(SiO2)/s) exposure. Device modeling shows that such a difference in screen-oxide N-ox is enough to account for the enhanced low-rate gain degradation often observed in bipolar devices, due to the similar to exp (N-ox(2)) dependence of the excess base current. At the higher rates, TSC measurements reveal a similar to 10% decrease in trapped-hole density over low rates. Also, at high rates, up to similar to 2.5-times as many trapped holes are compensated by electrons in border traps than at low rates for these devices and irradiation conditions. Both the reduction in trapped-hole density and increased charge compensation reduce the high-rate midgap shift. A physical model is developed which suggests that both effects are caused by time-dependent space charge in the bulk of these soft oxides associated with slowly transporting and/or metastably trapped holes (e. g., in E(delta)' centers). On the basis of this model, bipolar transistors and screen-oxide capacitors were irradiated at 60 degrees C at 200 rad(SiO2)/s in a successful effort to match low-rate damage. These surprising results provide insight into enhanced low-rate bipolar gain degradation and suggest potentially promising new approaches to bipolar and BICMOS hardness assurance for space applications.

The gain degradation of modern bipolar transistors was investigated for dose rates ranging from 0.01 similar to 2000 rad(SiO2)/s; Five different radiation sources were used for the exposures: three Co-60 sources, a 10-keV x-ray source, and a Cs-137, source. The C-137 exposures at 0.01 rad(SiO2)/s are two orders of magnitude lower in dose rate than any previous irradiations for this process and thus facilitate comparison to the device response in space. Low-dose-rate gain degradation exceeds high-dose-rate degradation for total doses less than 1 Mrad(SiO2), consistent with previous reports. For the first time, the gain degradation is demonstrated to be equivalent for dose rates between 0.01 and 10 rad(SiO2)/s, suggesting that the dose-rate response saturates at similar to 10 rad(SiO2)/s for the devices studied in this work. On the basis of a recent model, high-dose-rate irradiations at 60 degrees C were performed and found to be consistent with the room-temperature, low-dose-rate, saturated response. These results suggest several promising new approaches to bipolar space-qualification testing.

Thermally-stimulated-current and capacitance-voltage measurements reveal enhanced hole trapping in bipolar spacer-oxide capacitors irradiated at 0 V at low dose rates. Possible mechanisms and implications for bipolar low-rate response are discussed.

The effects of the midgap-level interface trap density and net oxide charge on the total-dose gain degradation of a bipolar transistor are separately identified. The superlinear dose dependence of the excess base current is explained.

Different hardness-assurance tests are often required for advanced bipolar devices than for CMOS devices. In this work, the dose-rate dependence of bipolar current-gain degradation is mapped over a wide range of dose rates for the first time, and it is very different from analogous MOSFET curves. Annealing experiments following irradiation show negligible change in base current at room temperature, but significant recovery at temperatures of 100 degrees C and above. In contrast to what is observed in MOSFET's, irradiation and annealing tests cannot be used to predict the low-dose-rate response of bipolar devices. A comparison of x-ray-induced and Co-60 gamma-ray-induced gain degradation is reported for the first time for bipolar transistors. The role of the emitter bias during irradiation is also examined. Implications fdr hardening and hardness assurance are discussed.

The primary degradation in modern bipolar transistors that are subjected to ionizing radiation is a reduction in current gain. There are many factors that influence the total-dose response of bipolar transistors, including emitter bias, transistor polarity, emitter technology, emitter geometry, base design, and dose rate. The effects of each of these factors are investigated. Physical mechanisms consistent with the observed effects are described.

Two models are presented to describe the immediate environment surrounding negatively charged contaminants in an idealized argon plasma. The first model uses Poisson’s equation to determine the contaminant charge and voltage. This model predicts a critical radius of the order of the Debye length below which Poisson’s equation is no longer valid. Below the critical radius and for contaminant radii much less than the Debye length, the Coulomb potential is used to find the contaminant charge and voltage. Both models predict negative charges on the order of 10−14 C, and voltages on the same order of magnitude as the electron energy.

Ionizing radiation induced gain degradation in microcircuit bipolar polysilicon and crystalline emitter transistors is investigated. In this work, C-60 irradiation testing was performed on bipolar test structures. The effects of collector bias, dose rate, and anneal temperature are discussed. Major differences in the radiation response of polysilicon emitter transistors are demonstrated as a function of dose rate. The worst-case gain degradation occurs at the lowest dose rate complicating hardness assurance testing procedures. The dose rate and anneal data suggest that MIL-STD-883B Test Method 1019.4 is non-conservative for polysilicon emitter transistors, which show enhanced radiation hardness over the crystalline emitter transistors.

The perimeter dependence of ionizing-radiation-induced increases in base current in both poly-emitter and crystalline-emitter devices is examined. The increase in base current occurs at the surface near the emitter-base junction. In the poly-emitter devices, the increase in base current is due to a buildup of interface states. In the crystalline-emitter devices, the increase in base current is caused by both an increase in the interface-trap density and a spread in the field-induced depletion layer. The perimeter dependence is shown to be similar to that caused by electron-beam damage and hot-carrier stressing