The surface-induced ordering of liquid crystals (LC) has been harnessed to detect a wide range of chemical and biological stimuli. In most sensor designs, the information-rich response of the LC is transduced from an analyte-triggered change in the out-of-plane orientation of the LC. Quantifying the out-of-plane LC orientation, however, is often complicated by simultaneous changes in the in-plane orientation of the LC when using polarized light for transduction. Here we introduce a sensing approach that combines a dichroic dye-doped LC (DDLC) with unpolarized light and a photodiode to achieve precise quantification of analyte-driven changes in the out-of-plane orientations of LCs. We benchmark the performance of the new methodology against polarizer-based approaches using a model amphiphilic analyte in aqueous solution and show that the DDLC provides a substantial reduction in the coefficient of variation (300% to less than 5%), an enhanced analytical sensitivity (0.16 to 3.73 μM-1), and an expanded dynamic range. In addition, when used to sense concentration gradients of analytes, the new approach distinguishes differences as small as 0.03 μM/μm over a dynamic range of 2 μM/μm, significantly outperforming conventional polarizer-based approaches that detect differences of 0.3 μM/μm over a dynamic range of 0.6 μM/μm. Overall, we conclude that the improved sensing performance and simpler implementation (no polarizers) of the DDLC approach, as compared to conventional LC sensors based on crossed-polars, will facilitate the deployment of LC sensors in diverse contexts, including the development of high-throughput screens for chemical formulations.

The development of high-bandwidth applications, including multi-gigabit communication and radar imaging, demands faster processing. However, in the microwave regime, where frequencies exceed clock rates, sampling and computation become challenging. Here we report an integrated microwave neural network for broadband computation and communication. Our microwave neural network operates across tens of gigahertz but is reprogrammed with slow megabits per second control bitstreams. By exploiting strong nonlinearity in coupled microwave oscillations, it expresses its computation in a narrower spectrum, enabling easy read-out. The system searches bit sequences in multi-gigabits per second data and emulates digital functions without custom circuits. It accelerates radio-frequency machine learning by classifying encoding schemes and detecting frequency shifts to track flight trajectories from radar. The microwave neural network is fabricated with standard complementary metal–oxide–semiconductor technology. It occupies a sub-wavelength footprint of 0.088 mm2 on chip and has a sub-200-mW power consumption, supporting integration in a general-purpose analogue processor. A low-power microwave neural network fabricated using complementary metal–oxide–semiconductor technology can perform broadband computations using a slow control mechanism.

Precise on-chip phase control of microwave transmission is critical to today's signal processing and wireless communication electronics. Thus far, achieving even modest phase-shifting resolution has involved a complex mix of semiconductor switches and passive electromagnetic structures. These delay circuits operate near resonances that heavily attenuate and distort signals, limiting modulation bandwidth. In this article, we introduce a mechanism whereby miniature waveguide reflectors based on coupled resonances can be reprogrammed to evade loss. Central to their operation is that loss from these resonances is confined to low frequencies, while at high frequencies, the waveguides' reflectivity is maximized and broadband phase variations, induced by those resonances, still persist. Since performance in the low-loss post-resonance spectrum is largely agnostic to the number of switches, ultra-fine digital tuning is possible. This breaks the historical tradeoff between loss and precision. When inserted in a reflective-type structure, a phase resolution of under 0.3 (degrees) is achieved, surpassing state-of-the-art CMOS circuits by over three orders (bits) of magnitude while incurring only 5 +/- 2.5 dB of loss over the 20-30 GHz 5G MIMO band. The phase-shifter is highly linear, with an input third-order intercept point (IIP3) of over 25 dBm. Moreover, it consumes no DC power and occupies a sub-wavelength footprint of 0.064 mm(2) in a 28 nm Fully Depleted Silicon-on-Insulator (FDSOI) CMOS platform. This makes it an optimal candidate for seamless integration in on-chip multi-gigabit data links, radio astronomy transceivers and control hardware for millimeter-wave qubits.

Increasingly functional microscopic machines are poised to have massive technical influence in areas including targeted drug delivery, precise surgical interventions, and environmental remediation. Such functionalities would increase markedly if collections of these microscopic machines were able to coordinate their function to achieve cooperative emergent behaviors. Implementing such coordination, however, requires a scalable strategy for synchronization—a key stumbling block for achieving collective behaviors of multiple autonomous microscopic units. Here, we show that pulse-coupled complementary metal-oxide semiconductor oscillators offer a tangible solution for such scalable synchronization. Specifically, we designed low-power oscillating modules with attached mechanical elements that exchange electronic pulses to advance their neighbor’s phase until the entire system is synchronized with the fastest oscillator or “leader.” We showed that this strategy is amenable to different oscillator connection topologies. The cooperative behaviors were robust to disturbances that scrambled the synchronization. In addition, when connections between oscillators were severed, the resulting subgroups synchronized on their own. This advance opens the door to functionalities in microscopic robot swarms that were once considered out of reach, ranging from autonomously induced fluidic transport to drive chemical reactions to cooperative building of physical structures at the microscale.

Precise phase control of microwaves and millimeter waves is critical for today's wireless communication and signal processing electronics. For decades, achieving even modest phase-shifting resolution has demanded a complex mix of transistor switches and passive electromagnetic structures. These true-phase delay, true-time-delay or quasi-true-time-delay circuits operate near resonances that heavily attenuate and distort signals, limiting transmission bandwidth. Despite numerous attempts, passive phase shifters have remained lossy and incompatible with high-channel-capacity beamforming, irrespective of the semiconductor fabrication process. In this article, we introduce a mechanism whereby waveguide reflectors based on coupled resonances can be reprogrammed to evade loss. Central to their operation is that loss from internal resonances is confined to low frequencies, while at high frequencies, their reflectivity is maximized and broadband phase variations, induced by those resonances, still persist. Since performance in the low-loss post-resonance spectrum is largely agnostic to the number of switches, ultra-fine digital tuning is possible. This breaks the historical tradeoff between loss and precision to achieve resolution surpassing state-of-the-art integrated circuits by over three orders (bits) of magnitude. The device does not distort the transmitted signal and consumes no power. Moreover, the chip occupies a sub-wavelength footprint in a Complementary Metal Oxide Semiconductor platform. This makes it an optimal candidate for seamless integration in on-chip multi-gigabit data links, radio astronomy transceivers and control hardware for millimeter-wave qubits.

Massive-data connectivity has driven the need for efficient, directed communications through beamforming arrays1-10. Delay elements are critical in any beamforming signal chain. However, these elements impose fundamental limits on size, channel capacity, power efficiency and effective isotropic radiated power11. Although passive phase shifters do not consume DC power, they suffer from narrow bandwidth, poor phase resolution and low power-handling capacity. They introduce a beam squint, in which different frequency components experience different time delays, blurring signals so that they cannot be resolved. This severely limits the data rate of the wireless link, that is, its channel capacity. Although true time delay (TTD) elements12 solve this problem and service a broad bandwidth, they comprise wavelength-scale transmission lines, making them prohibitively area-inefficient for modern semiconductor processes. Here we address this long-standing problem by introducing a quasi-true time delay (Q-TTD) that miniaturizes TTD elements and breaks fundamental channel-capacity limits of these wireless links. We demonstrate this mechanism for a microwave device implemented in a complementary metal-oxide-semiconductor (CMOS) technology. Key to shrinking the footprint is a reflective-type phase-shifting structure with 3D variable TTD reflectors within a sub-wavelength footprint. This achieves ultra-broadband phase tuning by using them to vary the length of the waveguide's path to ground. They produce a delay-to-area ratio that yields a substantially higher on-chip channel capacity compared with existing state-of-the-art methods. This component, when integrated in arrays, enables high-resolution imaging and low-squint beamforming for wideband communication, on-chip radar and other applications. A quasi-true time delay is demonstrated for a microwave device implemented in a CMOS technology to miniaturize true-time-delay components of beam-steering systems, addressing the fundamental channel-capacity limitations and increasing data transmission in wireless communications.

Shape morphing is vital to locomotion in microscopic organisms but has been challenging to achieve in sub-millimetre robots. By overcoming obstacles associated with miniaturization, we demonstrate microscopic electronically configurable morphing metasheet robots. These metabots expand locally using a kirigami structure spanning five decades in length, from 10 nm electrochemically actuated hinges to 100 μm splaying panels making up the 1 mm robot. The panels are organized into unit cells that can expand and contract by 40

There has been a resurgence of interest in vector architectures evident by recent adoption of vector extensions in mainstream instruction set architectures. Traditionally, vector engines leverage this abstraction by exploiting its inherent regularity to increase performance and efficiency. Recent work on SRAM-based compute-in-memory has shown promise in reducing the area overhead of these engines. In this work, we propose ephemeral vector engines (EVE) where we leverage SRAM-based compute-in-memory techniquesas well as bit-peripheral computations to facilitate efficient vector execution. EVE uses a novel approach of bit-hybrid execution, striking a balance between throughput and latency. Evaluated on the Rodinia and RiVEC benchmark suites, EVE achieves almost 8× speed-up compared to an out-of-order processor and 4.59× compared to an integrated vector unit. EVE achieves speed-ups comparable to an aggressive decoupled vector unit and increases the area-normalized performance by over 2 ×. By repurposing SRAM arrays in the L2 cache to create ephemeral vector execution units, EVE is able to efficiently achieve high performance while incurring as little as 11.7% area overhead.

Practical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interference cancellation circuit to enable pass-band, analog SIC in an IBFD system. Analog SIC is limited by several hardware constraints and design choices, including finite tap-delay resolution, non-negative tap constraints, and bit precision quantization. We characterize the performance impact of each of these limitations as a function of signal bandwidth, carrier frequency, bit precision, and other system design parameters. We further characterize the achievable system performance under all of these limitations combined. We simulate several realistic examples to illustrate the relationship between the achievable self-mitigation performance and various system design choices. We implement a simple constrained optimization algorithm informed by these results to optimize the tap-delay weights of the analog circuit under these system constraints. We simulate the achievable mitigation performance and demonstrate as much as 45 dB of analog-domain, self-interference mitigation of a wide-band signal with realistic system configurations.

In this paper, we demonstrate a prototype system for path independent local oscillator (LO) synchronization of a distributed beamformer in wireless ad hoc networks. The system contains a low power full duplex (FD) transceiver IC, a RF phase interpolator IC, and a CDMA encoder/decoder to realize a conjugate loop and synchronize the LO’s of two RF nodes. Both ICs were fabricated in 180nm CMOS technology. The FD transceiver IC consumes 69mW at 700MHz and the RF phase interpolator IC consumes 75mW at 1.4GHz. Using the low power ICs, we demonstrate a simple, lightweight, and robust methodology to synchronize two LO’s with an average phase precision of 2.1° and 94% maximum beamforming gain using RF only transmissions via a single antenna per node.

This study investigates processing techniques to alleviate the impact of hardware imperfections for in-band full-duplex (IBFD) systems. The studied IBFD model considers a multi-tap digitally controlled analog filter to provide RF cancellation. With precise optimization, non-negative tap weights reconstruct the multi-path channel to mitigate the self-interference (SI). In our simulation study, the SI cancellation significantly degrades when the initial tap weights are optimized without accounting for the timing errors induced by hardware imperfections. Therefore, we develop a new adaptive algorithm to tune the tap weights and recover the performance degradation caused by the timing errors. Our results indicate that the proposed data-driven method compensates for the timing offsets. Additionally, by considering the finite bit depth of the non-negative tap weights the performance improves compared to when there are no timing errors present.

Due to the rapid adoption of mmW bands for 5G communications, the complexity of transceiver systems must increase to operate over ever further separated frequency bands. In more traditional sub-6-GHz bands, software-defined radio (SDR) techniques allow for unified, multiband RF front ends; however, maintaining this ultrawideband or ultrawide tunable operation at mmW frequencies poses many challenges. One such challenge is ultrawideband mmW frequency synthesis, a challenge for which we present a new lumped/distributed tunable LC structure, the compact tunable transmission line (CTTL). In this article, we observe how the CTTL enables a state-of-the-art −203-dBc/Hz FOM $_{T}$ multioctave tunable mmW VCO, achieving a >4 octave tuning range with output up to 51 GHz. To analyze the CTTL in comparison to conventional tunable LC VCOs, we develop a new phase noise and oscillator figure-of-merit (FOM) model that provides an analysis framework for wide LC tuning. This new model is verified against simulation for conventional tuning and then is used to show how the CTTL provides a higher $Q$ and, therefore, better oscillator performance compared with existing LC tuning methods in the case of multioctave frequency synthesis. This analysis is then confirmed by the measured results of the manufactured CTTL VCO.

Bluetooth Low Energy (BLE) mesh networks enable diverse communication for the Internet of Things (IoT). However, existing BLE mesh implementations cannot simultaneously achieve low-power operation, symmetrical communication, and scalability. A major limitation of mesh networks is the inability of the BLE stack to handle network-scalable time synchronization. Pulse-coupled oscillators (PCOs) have been studied extensively and are able to achieve fast and reliable synchronization across a range of applications and network topologies. This paper presents a lightweight physical (PHY) layer accelerator to the BLE stack that enables scalable synchronization command with a PCO. The accelerator is a fully digital solution that can be synthesized with only the standard cells available in any silicon technology. This paper provides a detailed analysis of PCO-based BLE mesh networks and explores per-node system-level requirements. Finally, the analytical results are validated with measurements of a custom radio node based on the ubiquitous AD9364 transceiver.

Emerging applications such as autonomous vehicles and urban air mobility (UAM) rely on radar, communications, and positioning, navigation, and timing (PNT) capabilities, all of which compete for limited spectral resources. In-band, full-duplex (IBFD) systems promise better spectral efficiency but also introduce significant self-interference. In this paper, we discuss a combination of self-interference cancellation approaches for IBFD, joint radar-communications systems in the context of automated vehicles and urban air mobility. We propose and simulate an analog suppression technique and characterize its performance under realistic hardware limitations including bit precision, channel delay spread, time alignment, and carrier frequency.

Multi-antenna wireless communication improves spectral efficiency by reusing frequencies at different locations in space using beamforming and spatial multiplexing. In the past, research has extensively focused on dynamically reusing unused frequency bands to optimize spectrum usage, but methods that identify unused resources in space appear to be unexplored. In this paper, we propose a sample-efficient whitespace detection pipeline for multi-antenna radio-frequency (RF) transceivers that detects unused resources in both frequency and space. Our spatio-spectral whitespace detection pipeline relies on multi-antenna nonuniform wavelet sampling, which identifies unused frequencies in space at sub-Nyquist sampling rates. We demonstrate the efficacy of our approach via system simulations and show that reliable spatio-spectral whitespace detection is possible with $16 \times $ lower sampling rates than methods relying on Nyquist sampling.

The adoption of 5G standards requires new wireless devices to support not only traditional RF bands, but also mmW frequencies up to and beyond 40GHz. Such mmW hardware typically requires narrowband LC resonant circuits for efficient, low-noise operation. For widely-tuned software-defined systems, multi-octave LC tuning is not achievable due to the lack of a practical, solid-state tunable inductive element, limiting the mmW performance of software-defined radios. In this paper, we present a novel, compact, lumped/distributed LC-equivalent resonator capable of continuous tuning over more than four octaves in frequency while maintaining a practical quality factor in an unmodified 28nm FDSOI CMOS for the first time. This resonator is used to implement a cross-coupled LC VCO tunable from 3.1 to beyond 51GHz requiring less than 0.208mm 2 of area, less than 8mW of power, and achieving a state of the art peak FOM T for multi-octave tunable mmW VCOs of −198.2dBc/Hz.

We present a tunable LNA for software defined radio based on a compact, tunable transmission line (CTTL) element. The CTTL acts as a passive, widely tunable LC resonance in a cascoded, common source LNA to implement an instantaneously narrowband, multi-octave tunable LNA. The resulting circuit, fabricated in 65nm CMOS, is tunable from 3.5-20GHz, and consumes 12 mW with gain >12dB, ≥ -9.6dBV in-band OP1dB, and OOB B1dB up to 31dB higher than the in-band B1dB due to the CTTL-tuned LC filtering. The CTTL-tuned LNA represents a more blocker-tolerant approach to achieving high frequency, software-defined LNAs without significant compromises in other LNA performance metrics.

This paper presents a comparison of array-level performance of non-volatile SOT-MRAM and SOTFET-RAM to conventional 6T CMOS SRAM using a specially developed simulation suite that merges physics-based compact models and layout-based parasitic extraction. Unlike prior work, our characterization framework generates a full layout of the memory array including all peripheral logic and routing. The framework uses an industry-standard parasitic extraction tool to generate the full netlist including parasitics which is then simulated using compact models for the appropriate emerging non-volatile device. Using this framework, we show about 1.8x energy savings for total read operations and write operations, and 2x area savings for the SOT-based memories relative to a comparable CMOS SRAM for a $256\times 128$ array size. Our unique full-layout approach also enables important insights that challenge conventional wisdom based on higher-level modeling.