Spin-based silicon quantum dots are an attractive qubit technology for quantum information processing with respect to coherence time, control, and engineering. Here we present an exchange-only Si qubit device platform that combines the throughput of CMOS-like wafer processing with the versatility of direct-write lithography. The technology, which we coin SLEDGE, features dot-shaped gates that are patterned simultaneously on one topographical plane and subsequently connected by vias to interconnect metal lines. The process design enables non-trivial layouts as well as flexibility in gate dimensions, material selection, and additional device features such as for rf qubit control. We show that the SLEDGE process has reduced electrostatic disorder with respect to traditional overlapping gate devices with lift-off metallization, and we present spin coherent exchange oscillations and single qubit blind randomized benchmarking data.

We report the first generation of GaN MMIC circuits that are based on the latest generation of (ft > 320 GHz and fmax > 580 GHz) [1] GaN Transistors. The reported broadband Ka-band (27 GHz - 40 GHz) GaN LNA MMIC's have Noise Figure (NF) as low as 1 dB measured at a frequency of 37 GHz, NF <; 2 dB with >24dB of gain across 28 GHz- 39.2 GHz frequency range, and a very broad range of usable DC bias conditions (Vd: 0.6V - 4V; Pdc: 5 mW- 310 mW). This is to the best of our knowledge the lowest NF reported for GaN LNA in this frequency band.

We report the state-of-the-art performance of deep-submicrometer gate length dual-gate GaN HEMTs and cascode GaN HEMTs with 10× reduced gate-to-drain feedback capacitance compared with single-gate GaN HEMTs. With 150-nm gate length field-plated gate structures, these GaN HEMTs demonstrated improvement of small-signal gain by 10 dB, compared with single-gate GaN HEMTs. Large-signal load-pull measurements showed peak power-added-efficiency (PAE) of 71%-74% without harmonic tuning at 10 GHz, up to a measured continuous-wave output power level of 2.3-2.5 W. The 74% PAE is very close to a theoretical maximum PAE of 78.5% without harmonic tuning. Compared with single-gate GaN HEMTs, both the dual-gate and cascode GaN HEMTs offer~10% improvement in peak PAE at the output power of 2.3-2.5 W.

In this letter, we discuss a novel asymmetric field plate structure utilizing a slanted field plate (FP) engineered to appropriately distribute the electric field on GaN high-electron mobility transistors (HEMTs) scaled for low-loss, high-speed power switch applications. A uniform electric field distribution achieved with the slant FP enables an optimum device design, where a low-dynamic ON-resistance (Ron,dyn) and high breakdown voltage are obtained simultaneously by minimizing the gate-drain distance. The optimized FP design demonstrated a low Ron,dyn of 2.3 (2.1) Ω-mm at a quiescent drain voltage of 50V in E-mode (D-mode) HEMTs with a breakdown voltage of 138 V (146 V). The corresponding high-frequency performance of E-mode (D-mode) HEMTs of peak fT/fmax = 41/100 GHz (53/100 GHz) yielded a decent Ron,dyn×Qg product in the range of 31.0-34.5 (28.0-33.3) mQ-nC. This new slant FP technology combined with scaled epitaxial structure (for short Lg) and reduced access resistances, using n+ GaN ohmic contacts, greatly enhances performance and design flexibility of high-speed, low-loss, GaN power switch devices.

We provide an overview of key challenges and technical breakthroughs that led to development of highly scaled GaN HEMT's having ft > 400 GHz and fmax > 550 GHz and the corresponding IC process. These highly scaled GaN devices have 5 times higher breakdown voltage than transistors with similar high frequency RF power gain in other semiconductor systems (Si, SiGe, InP, GaAs). We also report performance of the first generation of MMIC power amplifiers (PAs) that utilize these highly scaled devices. The power added efficiency (PAE) of 59% measured at a frequency of 32 GHz, bias of 3 V and output power of 24.3 dBm of the first generation Ka-band MMIC PAs that were built using these highly scaled GaN devices, represent a significant improvement in PAE over values reported for other semiconductor technologies at this frequency band as well as for Ka-band MMICs built in lower frequency GaN nodes. Presented data suggest that highly scaled GaN transistors are excellent candidates for MMIC PAs for next generation 28 GHz, 39 GHz, and higher frequency 5G mobile bands, because they would greatly extend battery lifetime in mobile handsets, due to their superior PAE compared to competing semiconductor technologies.

We report zero-bias millimeter-wave and sub-THz detection using graphene FETs up to 220 GHz and graphene heterostructure diodes with reduced 1/f noise in direct detection. This detection leveraged the nonlinearity of the channel resistance through resistive field-effect transistor mixing. At a 50 ohm load, measured device responsivity was 70 V/W at 2 GHz to 33 V/W at 110 GHz. The measured noise power of the graphene FETs was ~7.5 × 10 -18 V 2 /Hz at zero-bias. The NEP at 110 GHz was estimated to be ~80 pW/Hz 0.5 . A linear dynamic range of >40 dB was measured, providing 15 - 20 dB greater linear dynamic range compared to conventional CMOS detectors at the transistor level.

We report millimeter-wave and sub-terahertz detection using graphene FETs up to 220 GHz at zero-bias to reduce 1/f noise. Detection leveraged the nonlinearity of the channel resistance through resistive field-effect transistor mixing for high-dynamic range. At a 50-Ω load, measured detection responsivity was 70 V/W at 2 GHz to 33 V/W at 110 GHz. The measured noise power of the graphene FETs was ~7.5 ×10 -18 V 2 /Hz at zero-bias. Noise equivalent power at 110 GHz was estimated to be ~80 pW/Hz 0.5 . A linear dynamic range of > 40 dB was measured, providing 15-20 dB greater linear dynamic range compared to conventional CMOS detectors at the transistor level. The emerging graphene heterostructure diodes offer the RC limited cutoff frequency (f c ) of 2.9 THz with the noise equivalent power of ~ 8 pW/Hz 0.5 at 200 GHz due to its small junction-capacitance and diode nonlinearity.

This letter reports record RF performance of deeply scaled depletion-mode GaN-high-electron-mobility transistors (GaN-HEMTs). Based on double heterojunction AlN/GaN/AlGaN epitaxial structure, fully passivated devices were fabricated by self-aligned-gate technology featuring recessed n(+)-GaN ohmic contact regrown by molecular beam epitaxy. Record-high f(T) of 454 GHz and simultaneous f(max) of 444 GHz were achieved on a 20-nm gate HEMT with 50-nm-wide gate-source and gate-drain separation. With an OFF-state breakdown voltage of 10 V, the Johnson figure of merit of this device reaches 4.5 THz-V, representing the state-of-the-art performance of GaN transistor technology to-date. Compared with previous E-mode GaN-HEMTs of similar device structure, significantly reduced extrinsic gate capacitance and enhanced average electron velocity are the key reasons for improved frequency characteristic.

This letter reports record RF performance of deeply scaled depletion-mode GaN-high-electron-mobility transistors (GaN-HEMTs). Based on double heterojunction AlN/GaN/AlGaN epitaxial structure, fully passivated devices were fabricated by self-aligned-gate technology featuring recessed n+-GaN ohmic contact regrown by molecular beam epitaxy. Record-high fT of 454 GHz and simultaneous fmax of 444 GHz w...

Like modern microprocessors today, future processors of quantum information may be implemented using all-electrical control of silicon-based devices. A semiconductor spin qubit may be controlled without the use of magnetic fields by using three electrons in three tunnel-coupled quantum dots. Triple dots have previously been implemented in GaAs, but this material suffers from intrinsic nuclear magnetic noise. Reduction of this noise is possible by fabricating devices using isotopically purified silicon. We demonstrate universal coherent control of a triple-quantum-dot qubit implemented in an isotopically enhanced Si/SiGe heterostructure. Composite pulses are used to implement spin-echo-type sequences, and differential charge sensing enables single-shot state readout. These experiments demonstrate sufficient control with sufficiently low noise to enable the long pulse sequences required for exchange-only two-qubit logic and randomized benchmarking.

A multilayer, low-parasitic interconnection scheme for highly scaled GaN high electron mobility transistors is reported. The fabrication process offers three Au interconnects embedded in benzocyclobutene (BCB) dielectric, with an integrated air-box in the active area in order to minimise the gate parasitic capacitances. With the addition of the air-box, it is demonstrated that the performance of t...

Highly scaled GaN T-gate technology offers devices with high ft/fMAX, and low minimum noise figure while still maintaining high breakdown voltage and high linearity typical for GaN technology. In this paper we report an E-band GaN power amplifier (PA) with output power (Pout) of 1.3 W at power added efficiency (PAE) of 27% and a 65-110 GHz ultra-wideband low noise amplifier (LNA). We also report the first G-band GaN amplifier capable of producing output power density of 296mW/mm at 180 GHz. All these components were realized with a 40 nm T-gate process (ft= 200 GHz, fMAX= 400 GHz, Vbrk > 40V) which can enable the next generation of transmitter and receiver components that meet or exceed performance reported by competing device technologies while maintaining > 5x higher breakdown voltage, higher linearity, dynamic range and RF survivability.

Electrically defined silicon-based qubits are expected to show improved quantum memory characteristics in comparison with GaAs-based devices due to reduced hyperfine interactions with nuclear spins. Silicon-based qubit devices have proved more challenging to build than their GaAs-based counterparts, but recently several groups have reported substantial progress in single-qubit initialization, measurement, and coherent operation. We report coherent control of electron spins in two coupled quantum dots in an undoped Si/SiGe heterostructure, forming two levels of a singlet-triplet qubit. We measure a nuclei-induced T2* of 365 {plus minus} 11 ns, an increase over similar measurements in GaAs-based quantum dots by nearly two orders of magnitude. This value for T2* is consistent with theoretical expectations for our estimated dot sizes and a natural abundance of 29Si.

In this letter, we present the first graphene FET operation for zero-bias resistive FET mixers, utilizing modulation of graphene channel resistance rather than ambipolar mixer operations, up to 20 GHz. The graphene FETs with a gate length of 0.25 mu m have an extrinsic cutoff frequency f(T) of 40 GHz and a maximum oscillation frequency f(MAX) of 37 GHz. At 2 GHz, the graphene FETs show a conversion loss of 14 dB with gate-pumped resistive FET mixing, with at least > 10-dB improvement over reported graphene mixers. The input third-order intercept points (IIP3s) of 27 dBm are demonstrated at a local oscillator (LO) power of 2.6 dBm. The excellent linearity demonstrated by graphene FETs at low LO power offers the potential for high-quality linear mixers.

Direct-coupled field-effect transistor (FET) logic inverters and 501-stage ring oscillators (ROs) are fabricated using highly scaled GaN heterojunction FET with gate lengths of 20 and 40 nm. A 40-nm gate-length E/D inverter has logic-low and logic-high noise margins of 0.465 and 1.59 V, respectively, and a logic voltage swing of 2.38 V measured at V-dd = 2.5 V. The corresponding 40-nm 501-stage RO frequency and stage delay are 0.067 GHz and 15 ps, whereas the frequency and stage delay of a 20-nm RO are 0.133 GHz and 7.5 ps. The yield of the 20-nm 501-stage RO circuits is 52% across a 3-in diameter wafer. With 1006 transistors, the 501-stage ROs represent the highest level of transistor integration to date for a GaN circuit, whereas the stage delay is the shortest reported for a GaN digital circuit.

In this paper, we report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures, a low-resistance n(+)-GaN/2DEG ohmic contact regrown by MBE, a manufacturable 20-nm symmetric and asymmetric self-aligned-gate process, and a lateral metal/2DEG Schottky contact. As a result of proportional scaling of intrinsic and parasitic delays, an ultrahigh f(T) exceeding 450 GHz (with a simultaneous f(max) of 440 GHz) and a f(max) close to 600 GHz (with a simultaneous f(T) of 310 GHz) are obtained in deeply scaled GaN HEMTs while maintaining superior Johnson figure of merit. Because of their extremely low on-resistance and high gain at low drain voltages, the devices exhibited excellent noise performance at low power. 501-stage direct-coupled field-effect transistor logic ring oscillator circuits are successfully fabricated with high yield and high uniformity, demonstrating the feasibility of GaN-based E/D-mode integrated circuits with >1000 transistors. Furthermore, self-aligned GaN Schottky diodes with a lateral metal/2DEG Schottky contact and a 2DEG/n(+)-GaN ohmic contact exhibited RC-limited cutoff frequencies of up to 2.0 THz.

We report the first experimental demonstration of a lateral graphene heterostructure field-effect transistor (HFET) at wafer scale, where the graphene heterostructure channel consists of epitaxial graphene (Gr)/fluorographene (GrF)/graphene (Gr). GrF is a widebandgap material, providing a potential barrier to lateral carrier transport. Gate bias modulation of the Gr/GrF/Gr barrier via an electric field effect results in normally-off enhancement-mode graphene HFETs with an ON-OFF switching ratio of 10(5) at room temperature. These devices also demonstrate excellent current-voltage saturation, providing a potential path for active RF applications.

We report on an experimental demonstration of graphene-metal ohmic contacts with contact resistance below 100 Ω µm. These have been fabricated on graphene wafers, both with and without hydrogen intercalation, and measured using the transmission line method. Specific contact resistivities of 3 × 10−7 to 1.2 × 10−8 Ω cm2 have been obtained. The ultra-low contact resistance yielded short-channel (source-drain distance of 0.45 µm) HfO2/graphene field effect transistors (FETs) with a low on-resistance (Ron) of 550 Ω µm and a high current density of 1.7 A/mm at a source-drain voltage of 1 V. These values represent state-of-the-art (SOA) performance in graphene-metal contacts and graphene FETs. This ohmic contact resistance is comparable to that of SOA high-speed III–V high electron mobility transistors.