The increased demand for SiC power MOSFETs requires gate dielectrics with low defect densities and high reliability under high electric field and temperature conditions. In this work, we examine how oxidant chemistry and deposition temperature affect the electrical properties of Al 2 O 3 /SiO 2 bilayer dielectrics formed in n-type 4H-SiC MOS capacitors. These structures consist of a thin SiO 2 interfacial layer, over which Al 2 O 3 is deposited via ALD using three different oxidants at a temperature of 150–350°C. C–V and temperature-dependent I–V (25–150°C) measurements show that the choice of oxidant influences the flat band voltage shift and leakage current density, with a process-dependent trade-off between optimizing each parameter. These findings highlight that precise control of oxidant chemistry during ALD is essential for balancing flat band voltage stability with leakage suppression, and that multilayer-specific conduction models are critical for accurately predicting high electric field leakage characteristics in advanced SiC gate stacks.

ZrO2 is a promising high-k dielectric for SiC power devices due to its favorable bandgap alignment with SiC. However, it exhibits low breakdown fields and excessively high leakage currents for thicker layers. This paper presents an approach to suppress this leakage current by integrating thin interlayers of Al2O3, Y2O3, or La2O3 into the ZrO2 film. These interlayers significantly reduce the charge carrier transport through ZrO2 films and, thereby, the leakage current of the stack. Among the investigated interlayers, Al2O3 shows the most pronounced effect, reducing the leakage of ZrO2-based thick films by 2 orders of magnitude and achieving a breakdown field of 7.4 MV/cm. This is comparable to the value measured for pure Al2O3 (7.7 MV/cm). These improvements can be attributed to the amorphous nature of the laminated oxide as the crystallization temperature could be increased from 350 °C for pure ZrO2 up to 750 °C for the nanolaminate. Notably, the dielectric constant of this optimized stack is 13, which is twice as high as that of pure Al2O3. No additional charge trapping due to the interlayers was detected by Capacitance-Voltage hysteresis measurements. Furthermore, by additional optimization of the stack's deposition conditions, the charge trapping was reduced by 50% compared to pure ZrO2 films.

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

Inconsistencies in the concentrations of unintentional donor impurities and free charge carriers in GaN/AlGaN layer stacks hosting a two-dimensional electron gas (2DEG) can be attributed to the measurement procedure and solely depend on the way in which the free charge carrier concentration is extracted. Particularly, when the 2DEG acts as the bottom electrode in capacitance versus voltage measurements, unphysically low concentrations of free charges are calculated. This originates from the depletion of the 2DEG and the accompanying disappearance of the bottom electrode. It is shown that, for the case of a defined (non-vanishing) bottom electrode, the levels of donor impurities and resulting free charges consistently match.

Insulated-gate GaN-based transistors can fulfill the emerging demands for the future generation of highly efficient electronics for high-frequency, high-power and high-temperature applications. However, in contrast to Si-based devices, the introduction of an insulator on (Al)GaN is complicated by the absence of a high-quality native oxide for GaN. Trap states located at the insulator/(Al)GaN interface and within the dielectric can strongly affect the device performance. In particular, although AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) provide superior properties in terms of gate leakage currents compared to Schottky-gate HEMTs, the presence of an additional dielectric can induce threshold voltage instabilities. Similarly, the presence of trap states can be detrimental for the operational stability and reliability of other architectures of GaN devices employing a dielectric layer, such as hybrid MIS-FETs, trench MIS-FETs and vertical FinFETs. In this regard, the minimization of trap states is of critical importance to the advent of different insulated-gate GaN-based devices. Among the various dielectrics, aluminum oxide (Al2O3) is very attractive as a gate dielectric due to its large bandgap and band offsets to (Al)GaN, relatively high dielectric constant, high breakdown electric field as well as thermal and chemical stability against (Al)GaN. Additionally, although significant amounts of trap states are still present in the bulk Al2O3 and at the Al2O3/(Al)GaN interface, the current technological progress in the atomic layer deposition (ALD) process has already enabled the deposition of promising high-quality, uniform and conformal Al2O3 films to gate structures in GaN transistors. In this context, this paper first reviews the current status of gate dielectric technology using Al2O3 for GaN-based devices, focusing on the recent progress in engineering high-quality ALD-Al2O3/(Al)GaN interfaces and on the performance of Al2O3-gated GaN-based MIS-HEMTs for power switching applications. Afterwards, novel emerging concepts using the Al2O3-based gate dielectric technology are introduced. Finally, the recent status of nitride-based materials emerging as other gate dielectrics is briefly reviewed.

In this paper, low temperature and gold (Au)-free Ta/Al-based ohmic contacts fabricated by sputtering on AlGaN/GaN heterostructures are demonstrated on 150 mm GaN-on-Si substrates. The Au-free manufacturing process of Ta/Al-based ohmic contacts implemented by sputtering on large area substrates is shown to give comparable results to conventional Ti/AI-based ohmic contacts and therefore to be suitable for the integration of GaN-based devices in the Si technology production lines. Homogeneous contact resistance (Rc) values with a low mean value of $1.2\ \Omega$ mm are obtained over the entire substrate using Ta/Al/TaN metal stacks annealed at 550 °C. Low temperature and Au-free Ta/Al/TaN ohmic contacts are also compared to conventional high temperature annealed and Au-containing Ti/AI-based ohmic contacts in terms of sheet resistance (Rsh) stability before and after passivation. The temperature dependence of Rcin both metal schemes is then investigated supporting different transport mechanisms and posing novel reliability challenges related to their integration in metal-insulator-semiconductor (MIS)-high electron mobility transistors (HEMTs). For this reason, the two ohmic contact schemes are integrated into MIS-HEMTs which are compared in terms of on-resistance (RDS, on) at high-temperature operation.

The presence of a 2D electron gas (2DEG) in GaN/Al x Ga 1– x N heterostructures with low aluminum mole fraction is found to depend on the residual background impurity concentration in the GaN/AlGaN layer stack. At a residual donor level of 2 × 10 16 cm −3 , a 2DEG is absent at 300 K in dark environment. Such a 2DEG can be generated at the GaN/AlGaN interface either by illumination with ultraviolet light or by applying an electrostatic potential. The latter results in inherently normally‐off switching characteristics of lateral field‐effect transistors.

Trap states at the dielectric/GaN interface of AlGaN/GaN‐based metal–insulator–semiconductor high electron mobility transistors (MIS‐HEMTs) can cause threshold voltage (Vth) instability especially under positive gate bias stress. Herein, the influence of O2 plasma surface preconditioning (SPC) before the atomic layer deposition of the Al2O3 gate dielectric and of N2 postmetallization anneal (PMA) after gate metallization on the Al2O3/GaN interface quality is investigated. The interface is characterized by multifrequency capacitance–voltage measurements which show a smaller frequency dispersion after the employment of SPC and PMA treatments with a reduction of the interface trap density Dit to a value in the order of 2 × 1012 cm−2 eV−1 near the conduction band edge. The effectiveness of SPC and PMA is demonstrated in Al2O3/AlGaN/GaN MIS‐HEMTs by pulsed current–voltage measurements which reveal improved Vth stability.

Gold-free Ta/Al-based ohmic contacts fabricated by sputtering on AlGaN/GaN heterostructures and annealed at low temperature were investigated. The presence of a thin AlN spacer layer at the AlGaN/GaN heterojunction is demonstrated to prevent the ohmic contact formation as shown by rectifying behavior after annealing. Ta as an additional capping layer on Al leads to a severe morphology degradation and subsequent deterioration of the metal stack after annealing at 600 degrees C due to strong Ta-Al alloying verified by transmission electron microscopy. Using the compound metal TiN as capping layer circumvents the alloy formation, thereby making the contacts much more stable under annealing. A low contact resistance of 0.8 omega mm was obtained using Ta/Al/TiN metal layers annealed at only 500 degrees C. The nature of the current transport was investigated by analyzing the temperature dependence of the specific contact resistance, which points towards a current path through the AlGaN barrier by thermionic field emission.

We report our investigations on HVPE grown GaN with thickness of $20 \mu m$ on MOVPE GaN/Sapphire templates. The important characteristics for the proposed electric functionalities as drift layer in vertical devices as GaN power MOSFETs are the surface morphology and the doping concentration of the HVPE grown layer, which are characterized by AFM and CV measurements on Schottky diodes, respectively. The surface topography is sufficiently flat for forming well-defined junctions in the following overgrowth. The unintentional doping concentration of the HVPE grown layer is approaching a suitable low level enabling the control of the intentional doping level for drift layers in power devices.

We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al2O3 dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices. Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.

Scanning spreading resistance microscopy (SSRM) with its high spatial resolution and high dynamic signal range is a powerful tool for two-dimensional characterization of semiconductor dopant areas. However, the application of the method is limited to devices in equilibrium condition, as the investigation of actively operated devices would imply potential differences within the device, whereas SSRM relies on a constant voltage difference between sample surface and probe tip. Furthermore, the standard preparation includes short circuiting of all device components, limiting applications to devices in equilibrium condition. In this work scanning dynamic voltage spreading resistance microscopy (SDVSRM), a new SSRM based two pass atomic force microscopy (AFM) technique is introduced, overcoming these limitations. Instead of short circuiting the samples during preparation, wire bond devices are used allowing for active control of the individual device components. SDVSRM consists of two passes. In the first pass the local sample surface voltage dependent on the dc biases applied to the components of the actively driven device is measured as in scanning voltage microscopy (SVM). The local spreading resistance is measured within the second pass, in which the afore obtained local surface voltage is used to dynamically adjust the terminal voltages of the device under test. This is done in a way that the local potential difference across the nano-electrical contact matches the software set SSRM measurement voltage, and at the same time, the internal voltage differences within the device under test are maintained. In this work the proof of the concept could be demonstrated by obtaining spreading resistance data of an actively driven photodiode test device. SDVSRM adds a higher level of flexibility in general to SSRM, as occurring differences in cross section surface voltage are taken into account. These differences are immanent for actively driven devices, but can also be present at standard, short circuited samples. Therefore, SDVSRM could improve the characterization under equilibrium conditions as well.

Gallium nitride (GaN) has emerged as an essential semiconductor material for energy-efficient lighting and electronic applications owing to its large direct bandgap of 3.4 eV. Present GaN/AlGaN heterostructures seemingly feature an inherently existing, highly-mobile 2-dimensional electron gas (2DEG), which results in normally-on transistor characteristics. Here we report on an ultra-pure GaN/AlGaN layer stack grown by molecular beam epitaxy, in which such a 2DEG is absent at 300 K in the dark, a property previously not demonstrated. Illumination with ultra-violet light however, generates a 2DEG at the GaN/AlGaN interface and the heterostructure becomes electrically conductive. At temperatures below 150 K this photo-conductivity is persistent with an insignificant dependence of the 2D channel density on the optical excitation power. Residual donor impurity concentrations below 10$^{17}$ cm$^{-3}$ in the GaN/AlGaN layer stack are one necessity for our observations. Fabricated transistors manifest that these characteristics enable a future generation of normally-off as well as light-sensitive GaN-based device concepts.

In this report, the operation of a normally-off vertical gallium nitride (GaN) metal-oxide field effect transistor with a threshold voltage of 5 V is demonstrated. A crucial step during device fabrication is the formation of the highly n-doped source layer. The authors infer that the use of molecular beam epitaxy (MBE) is highly beneficial for suppressing diffusion of the magnesium (Mg) p-type dopants from the body layer grown by metal-organic vapor phase epitaxy into the source cap. Repassivation of the previously activated Mg acceptors by a hydrogen out-diffusion treatment is suppressed in the ultrahigh vacuum growth environment. Structural and electrical data indicate that the defect density of the GaN substrate is currently limiting device performance much more compared to other effects like varying surface morphology resulting from fluctuations in III/N stoichiometry during the MBE growth.

In this report the influence of the growth conditions on the surface morphology of AlGaN/GaN heterostructures grown on sapphire-based and bulk GaN substrates is nondestructively investigated with focus on the decoration of defects and the surface roughness. Under Ga-rich conditions specific types of dislocations are unintentionally decorated with shallow hillocks. In contrast, under Ga-lean conditions deep pits are inherently formed at these defect sites. The structural data show that the dislocation density of the substrate sets the limit for the density of dislocation-mediated surface structures after MBE overgrowth and no noticeable amount of surface defects is introduced during the MBE procedure. Moreover, the transfer of crystallographic information, e.g. the miscut of the substrate to the overgrown structure, is confirmed. The combination of our MBE overgrowth with the employed surface morphology analysis by atomic force microscopy (AFM) provides a unique possibility for a nondestructive, retrospective analysis of the original substrate defect density prior to device processing.

We report on the fabrication and characterisation of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET), which utilizes a high-k dielectric covered trench gate and a top side drain contact. The processing technology has been developed to be easily transferrable to a truly vertical MOSFET on GaN bulk material, as targeted for high-voltage power switching applications. Device functionality is demonstrated by linear transfer characteristic with a decent ON/OFF current ratio of 6 orders of magnitude and clear normally-off operation.

Metal–insulator–semiconductor (MIS) capacitor structures were fabricated on AlGaN/GaN two-dimensional electron gas heterostructure material in order to investigate important aspects of the gate module of a corresponding MIS-high electron mobility transistor device. The process sequence started with an initial wet chemical surface treatment of the as-grown semiconductor material followed by an atomic layer deposition of Al2O3 (high-k first). The electrical analysis focused on the gate leakage current as well as on the shift of the threshold voltage (Vth) upon bias stress in the off- and the on-state regions. The high-k first samples showed much better Vth stability compared to lithographically processed samples, in which the high-k deposition was performed after ohmic contact formation and just before the gate electrode metallization. These results reflect a superior quality of the high-k/GaN interface for the processed structures according to the high-k first approach.

The p-doping of GaN is typically done with Mg. Because of its high ionization energy Mg is not completely ionized at room temperature. This has to be considered in simulations for defining characteristic values and designing devices, if p-GaN with Mg incorporation is involved. In this work the influence of simulation with a constant ionization rate in comparison to a model dependent non-uniform ionization rate on device characteristics of a vertical GaN-MOSFET is investigated. Furthermore the different simulation variants were verified by using literature data.