A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-dimensional plane strain analysis using the global-local technique, based on St. Venant's principle, is performed on the diagonal cross-section of the wafer. The thermal-mechanical modeling has shown that the shear stress Sxy at the micro-bump, compressive stress Sy at the interconnection and shear stress Sxy at the TSV are reduced for off-pad via as compared to on-pad via. This is because the CTE mismatch between the micro-bump and TSV is no longer effective when the TSV is offset. Also the work presented that the offset distance of the off-pad via does not have an impact to the compressive stress Sy and shear stress Sxy at the interconnection. There are also no significant changes in the shear stress Sxy at the TSV as the off-pad via moves outward to the die edge. As we knows that the bending stress Sx is a major factor contributing to die cracking due to coefficient of thermal expansion (CTE) mismatch. Our simulation results showed that the bending stress Sx of the top die and bottom die was not affected by increasing the offset distance of the off-pad via even to the die edge. Thus it is an advantage to plate the through-silicon-via away from the micro-bump to avoid stresses complication arises from CTE mismatch.

The use of flip-chip bonding technology on gold-tin (AuSn) microbumps for flip-chip packaging is becoming increasingly important in the electronics industry. Some of the main advantages of AuSn system over solder flip-chip technology are suitability for very fine pitch interconnection and fluxless bonding. Fluxless flip-chip assembly is in demand especially for medical applications and optoelectonics packaging. Here, we report the assembly process development of a silicon stacked module assembled with AuSn microbumps to meet the stringent reliability. The effects of bond pressure distribution, bond temperature and alignment accuracy were found to be critical in this stacked silicon using AuSn microbumps. A three-factor design of experiment was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on contact resistance and AuSn solder wetting on the electroless nickel and gold under bump metallization. Results showed that higher bond force is undesirable and contributes to passivation cracking and deformed AuSn joint with AuSn solder being squeezed out of the joint during bonding. The reliability result of the flip-chip assembly of stacked silicon module using AuSn microbumps was presented.

Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated for medical application and assessed its package level reliability. The chip level stack module is achieved by stacking two thin dies of different size and thickness together using flip chip technology with micro bump interconnects. Electrical simulations are carried out to obtain RLC parameters of micro bump interconnect and complete interconnection from daughter die to substrate. Mechanical simulations are also carried out to study the stress analysis on micro bumps and CSP bumps in the package and parametric study of stacked module package to study the effect of substrate material, underfill material die thicknesses on package reliability and warpage. Test chips are designed and fabricated with daisy chain test structures to access the reliability of the stack module. Pb-free (SnAg) micro bumps of 40 mum on daughter die wafers and eutectic SnPb solder CSP bumps of 200 mum height on mother die wafers are fabricated. Mother die and daughter die bumped wafers were thinned to 300 mum and 60 mum respectively using mechanical backgrinding method. These thin dies are stacked using chip to wafer flip chip bonding and underfill process is established for the micro bump interconnects. The assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and un-biased high accelerated stress test (uHAST) and results are presented.