Fine-grained Cu was developed through electroplating (ECP) optimization to enable low temperature Cu/dielectric hybrid bonding for advanced high-bandwidth memory (HBM) integration. Uniform sub-100 nm grains were achieved on blanket wafers and further optimized for 3 µm patterned bond pads to improve sidewall grain uniformity. Thermal stability studies show that the fine-grained Cu remains stable at 200 °C, while grain growth is activated at below 220 °C to promote interfacial diffusion during bonding. A chemical mechanical polishing (CMP) process achieving approximately 1 nm Cu dishing ensures intimate Cu contact for bonding. Void-free wafer-to-wafer and chip-to-wafer hybrid bonding were demonstrated with post-bond annealing below 220 °C. The optimized ECP condition establishes a robust and thermally stable process window suitable for advanced HBM hybrid bonding applications.

Copper (Cu) surface topography, galvanic corrosion at the Cu-barrier interface and Cu-to-dielectric bonding primarily due to the misalignment are the present critical challenges in achieving void-free hybrid bonding. Additionally, Cu surface oxidation and dishing remain key bottlenecks in enabling reliable Cu interconnections at low temperatures in Cu/dielectric (SiO₂) hybrid bonding. To overcome these limitations, here we introduced a fabrication strategy that integrates an ultrathin metal (titanium (Ti)) passivation layer selectively engineered for Cu bond pads while maintaining compatibility with the damascene process. Despite the presence of the passivation layer, the observed Cu diffusion across the bonding interface and improved electrical contact resistance provides direct evidence of enhanced interfacial interdiffusion and oxidation resistance. This approach offers a scalable and effective solution for mitigating fundamental challenges in Cu/SiO₂ hybrid bonding and holds strong potential for integration into three-dimensional heterogeneous packaging technologies, enabling low thermal budget processing at ≤ 250 °C for ≤ 1-2 hour.

With the rapid advancement of artificial intelligence applications, the demand for high-performance computing is continuously increasing. In recent years, hybrid bonding has emerged as a crucial packaging technology that enables higher bandwidth and interconnect density. The inter-die gap fill (IDGF) process integration approach has gained attention for heterogeneous integration of chiplets 2.5D/3D chip stacking architecture. The IDGF process flow involves a chip-to-wafer (C2W) hybrid bonding process, inter-die-gaps filling with thick dielectric materials, and planarization to form a reconstituted C2W HB wafer. The wafer thinning and backside hybrid bond pad formation are important steps to enable 3D chip stacking. This work focuses on the correlation between the C2W bonding void area and delamination and crack formation risk during the wafer thinning process. The present work also demonstrates the backside bond pad fabrication on the reconstituted C2W HB wafer. Finally, 3D chip stacking is demonstrated using the optimized integration process flow. Wafer warpage evolution for 1 to 8 die stacks is simulated for three different gap-fill materials to identify the critical step and mitigate warpage risks.

This work presents a systematic study of particle control and defect mitigation across the C2W hybrid bonding process flow. Study of wafer singulation and Raman spectroscopy reveal that the dominant source of particles on diced wafer is back-grinding tape’s adhesive residue. A polymer-targeted cleaning process was developed, achieving ~90% particle reduction. A comparison between different mechanical dicing methods confirmed dicing-before-grinding (DBG) as the preferred baseline. Potential contamination from plasma chamber and collet contact during chip handling were also examined.Bonder equipment and process optimizations were implemented to minimize particle transfer, reducing particle-induced voids. Non-particle-related voids were mitigated through control of bond wave propagation. A 5 μm size pad and 10 μm pitch test vehicle was designed to validate the integration. ~90% electrical connectivity yield is achieved with robust Cu–Cu joint. This work establishes an effective framework for contamination control and yield improvement in fine-pitch C2W hybrid bonding.

Stacking two high-performance, high-power dissipation logic chips requires new cooling solutions to address the associated thermal challenges. The incumbent remote heat sink cooling solution is incapable of extracting heat efficiently from two stacked chips. This paper presents a novel process development for a backside embedded two-phase colling solution to address the thermal challenge for two-stacked high-power chips. The novel process development includes via-first large TSV (30 × 300 μm), frontside RDL for heater and sensor elements, and backside microchannels (8 × 8 mm) with micro pin-fins (100 μm). Testing results show that chip-1 dissipates a heat flux of 157W/cm2 and chip-2 dissipates a heat flux of 187W/cm2 at coolant flow rate 0.699 L/min.

Hybrid bonding has become a critical solution to enable fine pitch direct copper-to-copper (Cu-Cu) interconnection. In conventional oxide/Cu hybrid bonding, success is contingent on wafer surface cleanliness. A significant challenge in chip-level bonding arises from silicon debris generated during the mechanical dicing process, which contaminates the wafer surface. This study introduces a lowtemperature-curable polymer dielectric designed for hybrid bonding using mechanically diced chips. The polymer provides excellent defect coverage and enhanced particle tolerance. We demonstrate polymer/Cu hybrid bonding on memory chips with dense 10 mu m pitch Cu bumps and known particle contamination. The polymer/Cu hybrid bonding alignment precision of less than 2 mu m is achieved. Additionally, the study explores the process window of polymer CMP and reveals that the bonding yield relation with the copper bump protrusion from the polymer surface.

Multi-Chip Stacking in Hybrid bonding approach involved the use of 50 mu m thin chip with double side hybrid bonding pads. Thin chip handling is very challenging in assembly process such as dicing, picking up the chip from dicing tape and bond on the target substrate or wafer due to weak die strength. In addition, hybrid bonding adds further challenges due to stringent requirements of hybrid bonding process such as cleanliness, particles free surface and low chip's warpage. Hybrid bonding voids at the bonding interface can be attributed to the entrapped particles or residue or trapped air. In this work, we explored the use of a soft curvature tool coupled with optimized bonding parameters to achieve void-less bonding in multi-chip stacking.

The requirement of 3D IC packages with very fine pitch interconnections are driven by the rapid advancement of High-Performance Computing, Artificial Intelligence, Internet of Things, and Electric Vehicle Controls, etc. Chip-to-Wafer Hybrid Bonding (C2W-HB) is the technology that enables Heterogeneous Integration (HI) of dissimilar chips (or chiplets) with such fine pitch interconnections. Current technology of multi-level 3D stacking of dies before encapsulation into a molded die package pose several challenges. High wafer and package warpage, bulky packages due to thicker die-stacks are some of them. Inter-Die Gap Filling (IDGF) process flow is currently being developed address some of these challenges. This process allows deposition of a thick dielectric in the inter-die gap and subsequent thinning of the dies to a much smaller thickness (< 20um). In this work we developed a parametric finite element model to perform digital design of experiments (DDoE) of wafer warpage. In this work we report simulations with a 2-Stack C2W-HB wafer model. Using this the effect of inter-die gap, IDGF thickness, film residual stress, and IDGF material are evaluated to guide the process team. The DDoE results show that the IDGF film thickness and residual stress are the most important parameters to manipulate the wafer warpage. In our on-going work this model is extended to multi-stack C2W-HB wafer warpage simulations.

In the realm of heterogeneous integration (HI) for chip-to-wafer (C2W) hybrid bonding, optimizing the plasma process is crucial for enhancing interfacial bonding and extending shelf-life. This study employs a design of experiment (DOE) methodology to fine-tune plasma process parameters, focusing on plasma power, gas mixture proportions, and process duration. Initial investigations on blanket dielectric and copper wafers allowed for isolation of plasma treatment effects on each material. Various gases, including oxygen, hydrogen, nitrogen, and argon, were tested individually and in mixtures to achieve optimal surface activation and bond strength. The refined plasma process was applied to hybrid bond pads, with bond strengths assessed through advanced surface characterization techniques such as water contact angle measurements, atomic force microscopy (AFM), and film stress measurements (FSM). This comprehensive approach has led to the development of an innovative plasma process that significantly enhances bonding reliability and performance, marking a substantial advancement in C2W hybrid bonding applications.

The rapid advancement of artificial intelligence applications is continuously increasing the demand for highperformance computing. Conventional interconnect technology based on micro bump has pitch scaling, reliability, and bandwidth density limitations. In recent years, hybrid bonding has emerged as an essential packaging technology that achieves higher bandwidth and interconnect density. Dielectric film quality is important in achieving sufficient interfacial bonding energy for hybrid bonding. Wafer-level and chip-level bows are critical for 2.5D/3D die stacking. The CTE mismatch of Cu, Si, and oxide films leads to severe die-level warpage, impacts die tacking, and results in die drop or extensive void formation. This study focuses on characterizing dielectric materials (film thicknesses and stress profiles) coupled with different volume fractions of Cu in RDL to optimize wafer-level bow and enable chip-to-wafer (C2W) hybrid bonding. The work is further extended to optimize the inter-die gap fill (IDGF) oxide stress profile to limit substrate wafer bow to meet the tool specifications. The optimized film profiles are expected to enable multi-chip 3D stacking on reconstituted C2W hybrid bonded substrate wafer.

For multi-chip stacking using Chip-to-Wafer (C2W) Hybrid Bonding (HB) technique, one prominent approach is Inter-Die Gap Filling (IDGF) method. A major challenge in IDGF flow is achieving cost-effective, crack-free planarization of the dielectric fill. Ensuring crack-free planarization requires the dielectric thickness to match or exceed the silicon die thickness. Although thinner silicon dies can lower planarization time and costs, their fragile nature complicates handling during assembly. This study presents a novel non-standard silicon Chemical Mechanical Planarization (CMP) process for C2W hybrid-bonded wafers. The novel CMP process enables precise die thinning, significantly reducing dielectric planarization costs while mitigating thin-die handling challenges. Custom-designed slurry additives and polishing pads effectively minimize die-edge rounding and chipping. Process conditions, slurry composition and CMP pads-were optimized to achieve high silicon removal rates with enhanced surface integrity. This approach offers a scalable solution to improve manufacturing efficiency and reliability in advanced multi-chip integration.

Chip-to-wafer (C2W) hybrid bonding is a promising packaging technology for bumpless, high-density interconnections. However, this approach presents several process challenges during pre-bond fabrication, such as the effects of the dielectric layer, die warpage, surface roughness, and Cu bond pad dishing, all of which impact bond yield. This study uses TEOS oxide and SiCN interface dielectric films to achieve void-free hybrid bonding. Based on the chosen dielectric films, the surface planarization process was optimized to meet a surface roughness of less than 0.3 nm. Cu pad dishing, with different process splits ranging from -1 to +7 nm, was investigated for its impact on bonding quality and electrical performance. Daisy chain resistance per link for 3 mu m/3 mu m HBI pad and 6 mu m pitch was measured to be 45 +/- 2mO whereas corresponding structures, Kelvin resistance was measured to be 20 +/- 3.5mO. A similar trend has been observed for 3 mu m/5 mu m HBI pad and 10 mu m pitch. Daisy chain resistance per link is 58 +/- 1.5mO and kelvin resistance is 22 +/- 2.0mO. For 10 mu m pitch, the daisy chain resistance was found to be more than 25% than the 6 mu m pitch. Overall, a cumulative yield probability exceeding 98% was achieved under the selected CMP process conditions.

This study explores the assembly process for RF-digital integration with 2.5 D through-silicon interposer technology., with a focus on evaluated on process approach, materials compatibility and thermal processing. Thin silicon interposer exhibit warpage during assembly processing, which can impact assembly accuracy. Despite these challenges, the full assembly process was successfully demonstrated.

To improve Chip-to-Wafer Hybrid Bonding yield, the mechanical dicing process was studied to reduce particles on the diced wafer. Particles or contamination, or bonding wave propagation, are known to cause a void between the bonding interfaces. A detailed analysis of the bonding surface is conducted. An investigation was carried out on the large-sized particle and identified that the source is tape adhesive from the backgrind and dicing processes. With optimisation of the back-grinding and subsequent cleaning process, the post-dicing particle is controlled under 500 count (size $>1.7$ um). As such, we have implemented respective remedies targeting the analysed outcome and have successfully achieved above 90% daisy chain connections.

There is increasing recognition that 3D IC promises tremendous performance advantage. However, thermal management technologies currently limit implementation. In this paper, we present the development of an embedded backside 2phase cooling technology that enables the dissipation of high power in two stacked chips, aimed at future HPC and AI applications. The test vehicle was designed and fabricated. Testing results show that chip-1 can dissipate a heat flux of 157W/cm(2) and chip-2 can dissipate a heat flux of 187W/cm(2) at coolant flow rate 0.699 L/min. This is the first demonstration of an embedded 2phase cooling solution for two stacked high-power chips.

The miniaturisation of semiconductor devices has driven the industry to explore 3D ICs to achieve significant performance improvements over 2D ICs. However, stacking high-performance logic chips with a limited thermal path dissipates considerable heat, making 3D IC cooling challenging. The present study establishes a 3D CFD-heat transfer model to test the efficacy of the embedded two-phase cooling technique to address the thermal management challenges in a two-stacked logic chips. The developed model is validated against existing literature. Afterwards, the model is used for carrying out parametric studies with varying flow rate in the range of 140 ml/min - 490 ml/min and chip size from 10 x 10 mm(2) - 30 x 30 mm(2). For two-stacked chips with dimensions of 10 x 10 mm(2), a maximum dissipated heat flux of 768.6 W/cm(2) is achieved for a flow rate of 490 ml/min. A dissipated power of 1693.9 W is achieved for two-stacked chips with dimensions of 30 x 30 mm(2) at a fixed flow rate of 140 ml/min, with a pumping power of 0.63 W.

The increasing demand for high radio frequency (RF) output power in advanced communication, radar, and high-resolution sensing applications drives the necessity for integrating III-V semiconductors within RF front-end modules. This integration aims for optimal performance through heterogeneous configurations of III-V and silicon technologies packaged compactly and cost-effectively. Gallium Nitride (GaN) and Gallium Arsenide (GaAs) devices are crucial for achieving the stringent efficiency and output power standards required in these applications. Fan-Out Wafer-Level Packaging (FOWLP) has emerged as a promising solution to meet the demands of high-speed, high-density RF front-end solutions. However, existing FOWLP methodologies, particularly mold-first approaches, face significant challenges regarding the integration of fragile RF structures due to thermal management and interconnect reliability issues. This paper proposes a RDLfirst approach that enhances robustness by mitigating risks associated with embedding delicate air-bridge structures while maintaining efficient chip-to-chip and chip-to-RDL interconnects. It presents detailed methodologies for both the mold-first and RDL-first FOWLP structures, including process flows and results from implementing the RDL-first technique.

Two types of RDL interposer packages, namely FOWLP and 2.5D FO-interposer have been fabricated with Fan-out packaging technology. Both interposers feature six layers of high-density Cu RDL and are of package size of 52 x 44 mm, accommodating 12 chiplets. These interposers are mounted on a 60 x 60 mm organic substrate. The fabrication process for both RDL interposers is detailed and discussed in this work and comparison is conducted focusing on the interposer warpage. The FOWLP exhibits an initial convex warpage of 213 µm and increases to 380 µm after assembled to organic substrate. In contrast, the 2.5D FO-interposer on organic substrate exhibits a low convex warpage of 36 µm increase to 100 µm after chiplets integration. The 2.5D FO-interposer approach demonstrated better warpage control throughout the assembly process, positioning it as a promising packaging solution that addresses key challenges in interposer technology, particularly in mitigating warpage concerns associated with larger packages.

This study employs a low thermal budget glass-to-silicon direct bonding process without interlayers to fabricate $200\mu \mathrm{m}$ thick crystalline silicon (c-Si) pillars processed on $300\text{mm}$ glass substrates. The process demonstrated robust bonding integrity, with no chip-off even after rigorous backgrinding procedures. Comprehensive investigations were conducted on the selection of glass substrates, the impact of cleaning processes on the bonding interface, and the optimization of these cleaning protocols. Additionally, lithography and etching processes were optimized on blank silicon wafers prior to their application on glass-bonded wafers. Challenges associated with handling glass on electrostatic chucks (ESC) were also addressed. Following these optimizations, a detailed process flow was developed for fabricating thick silicon pillars with aspect ratio ranging of 1:2. Surface and interface analyses were performed using confocal scanning acoustic microscopy, optical/laser profilometry, and X-SEM inspections. This fabrication flow shows significant potential in the fields of advanced packaging, optoelectronics, microfluidics, MEMS, and terahertz (THz) technologies.

3D packaging with stacked dies is widely explored as a future advanced packaging technology for applications involving high-performance computing and High Bandwidth Memory (HBM) devices. In this direction, chip-to-wafer (C2W) hybrid bonding is an emerging technology that offers high I/O and heterogeneous integration of chips. For HBM stacking, the hybrid bond pads need to be fabricated on both sides. The backside process involves the wafer going through a temporary bonding and debonding (TBDB) process, and thus, the thermal budget of the fabrication processes is limited up to 200 °C. Therefore, a low-temperature PECVD-deposited SiCN was evaluated as the dielectric material for backside fabrication. This article focuses on the process challenges and mitigation plans in thin Wafers fabrication on 300 mm silicon wafer using the revised integration flows to enable four to eight memory chip stacking.