The development of ultrafine-pitch microbumps and the thermal compression bonding (TCB) process for advanced 3-D stacking technology are discussed in this paper. Microbumps, consisting of Cu pillars and thin Sn caps with a pitch of 25 μm, are fabricated on an Si chip by the electroplating method. Total thickness of the Cu pillar and the Sn cap is 10 μm. Electroless nickel and immersion gold pads with a total thickness of 4 μm are fabricated on an Si carrier. TCB of the Si chip and the Si carrier is conducted on an FC150 flip-chip bonder, and a good joining with higher than 10-MPa die shear strength is achieved. After bonding, the bond line thickness between the Si chip and the Si carrier is filled with the selected capillary underfill material. Void-free underfilling is achieved with underfill materials which have a fine filler size. Ninety percent of the bonded samples can pass the thermal cycling test (-40/+125°C) with 1000 cycles and the highly accelerated temperature/humidity stress test (130°C , 85% RH) for 96 h.

Capsule endoscopy is a frontline medical diagnostic tool for the gastro intestinal tract disorders. During diagnosis, efficient localization techniques are essential to specify a pathological area that may require further diagnosis or treatment. This paper presents the development of a miniature tagging module that relies on a novel concept to label the region of interest and has the potential to integrate with a capsule endoscope. The tagging module is a compact thermo-mechanical actuator loaded with a biocompatible micro tag. A low power microheater attached to the module serves as the thermal igniter for the mechanical actuator. At optimum temperature, the actuator releases the micro tag instantly and penetrates the mucosa layer of a GI tract, region of interest. Ex vivo animal trials are conducted to verify the feasibility of the tagging module concept. X-ray imaging is used to detect the location of the micro tag embedded in the GI tract wall. The method is successful, and radiopaque micro tags can provide valuable pre-operative position information on the infected area to facilitate further clinical procedures.

With the increasing demand for system integration to cater to continuously increasing number of I/Os as well as higher operating frequencies, reconfigured wafer-level packaging, or embedded WLP (EMWLP) is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present low loss passives on EMWLP platform demonstrated in a 5.5-GHz band pass filter targeted for wireless local area network (WLAN) applications. To ascertain the feasibility of designing for low loss millimeter wave passives on EMWLP, transmission lines were designed and their loss characteristics investigated up to 110 GHz, which are reported here. Subsequently we demonstrate for the first time a narrowband low loss 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results. In addition, a temperature dependence characterization was performed on the 77-GHz filter, with little variation in the measured filter characteristics observed.

In this paper, a method of fabricating radio opaque silicon micro needles for tissue labeling applications is reported. Cylindrical shaped micro needles ranging from 7 × 7 to 11 × 11 arrays with a pitch varying from 60 μm to 100μm are fabricated in silicon using a three step mask process. A backside cavity is generated under DRIE for filling the radiopaque material. Barium sulphate is filled in and a biocompatible sealing is provided to hold the radiopaque material inside. The fabricated needles provide a better contrast enhancement under x-ray imaging.

Capsule endoscopes are effective diagnostic tools for the gastro intestinal tract disorders at patient's comfort. However the present capsule endoscopes lack efficient localization techniques to specify a pathological area that may require further diagnosis or treatment. This paper presents the development of a tagging module based novel method for the real-time localization of the site of interest. The tagging module consists of a bio compatible micro tag, compressed spring with a string latch and thermal igniter. The module can be integrated with the capsule endoscope and activated using an external trigger signal. On activation, the micro tag releases instantly and penetrates the mucosa layer of GI tract, region of interest. X-ray imaging is used to detect the location of micro tag embedded in GI tract wall. The radiopaque micro tags provide pre-operative valuable position information of the infected area to facilitate further clinical procedures.

In this paper a liquid cooling solution has been reported for 3-D package in PoP format. The high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via for electrical interconnection and through-silicon hollow via for fluidic circulation. Heat enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated 100 W of heat dissipation from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed.

A dry film photoresist was selected as the sacrificial material for a metal lift off process. However, a weak and inconsistent adhesion of the evaporated under bump metallurgy (UBM) and solder on the passivation surface was observed during the dry film stripping process. This problem may be due to the poor negative profile (88 to 89 degrees) of the patterned dry film side wall after dry film developing, resulting to inconsistent metal lift off. A few dry film predevelopment and post development parameters are identified and tested from the standard dry film development process, to obtain a negative profile of the dry film to be less than 84 degrees. After each test, cross section of the patterned dry film side wall is observed under a microscope to check if a negative profile is obtained. The 50 mu m thick dry film at 35mJ/cm(2) with other modifications of the process gives the best results

This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 x 10mm(2) micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100 mu m bump pitch and 1,124 I/O; the other micro-bumped chip had 50 mu m bump pitch and 13,413 I/O. The TSV interposer size is 25 x 25 x 0.3mm(3) with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 x 45mm(2) with 1-2-1 layer configuration, a ball-grid array (BGA) of 1 mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment.The objective of this paper was to incorporate two 8 x 10mm(2) micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.

Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated for medical application and assessed its package level reliability. The chip level stack module is achieved by stacking two thin dies of different size and thickness together using flip chip technology with micro bump interconnects. Electrical simulations are carried out to obtain RLC parameters of micro bump interconnect and complete interconnection from daughter die to substrate. Mechanical simulations are also carried out to study the stress analysis on micro bumps and CSP bumps in the package and parametric study of stacked module package to study the effect of substrate material, underfill material die thicknesses on package reliability and warpage. Test chips are designed and fabricated with daisy chain test structures to access the reliability of the stack module. Pb-free (SnAg) micro bumps of 40 mum on daughter die wafers and eutectic SnPb solder CSP bumps of 200 mum height on mother die wafers are fabricated. Mother die and daughter die bumped wafers were thinned to 300 mum and 60 mum respectively using mechanical backgrinding method. These thin dies are stacked using chip to wafer flip chip bonding and underfill process is established for the micro bump interconnects. The assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and un-biased high accelerated stress test (uHAST) and results are presented.

With the increasing demand for system integration to cater for continuously increasing I/Os as well as higher operating frequencies, EMWLP is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present the results of high quality passives on EMWLP platform that are benchmarked against high resistivity silicon (HiRSi). The passives were then demonstrated in two band pass filters targeted to operate in the IEEE 802.11a band, with electrical performances comparable to that of commercial IPDs. Using the same platform, the measured loss characteristics of transmission lines up to 110 GHz is reported. We also demonstrate for the first time a low loss narrowband 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results.

Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm times 10 mm times 0.4 mm and solder ball pitch of 0.4 mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 degC have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (-40 to 125degC), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (> 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.

In this paper, a process for embedding and interconnecting three dimensional (3D) thin chips stacked in multilayer dielectric at wafer level is presented. Chips of different dimensions are thinned to 30 ¿m thickness using conventional back-grinding and singulated by dicing. Thin chips of different dimensions were then stacked onto a silicon carrier and embedded in multilayer of pre-formed photo-dielectric film using a vacuum lamination process. Photo-lithography process was used to develop the micro-vias in the dielectric film and thin film metallization is used to form interconnection between the vertically stacked chips. Under bump metallization is processed on the fan-out region of the thin film metallization lines for board level connectivity. Finally, the silicon carrier is removed to release the embedded 3D stacked package. The embedded 3D stacked package fabricated has a thickness of 110 ¿m and electrical measurements shows good electrical connectivity between the 2 chips stacked and the fan-out metallization lines.

In this paper, we demonstrate the extraction of the effective dielectric properties of a new low-k thin film material, up to the millimeter wave region (110 GHz). This is achieved using a CPWG T-resonator. In literature, such a configuration has not been considered before, as a 50-Ohm structure is usually designed for the T-resonator. In this work, we show that using a non-50 Ohm structure has no influence on the extracted effective dielectric constant, which can be achieved within an accuracy of 4% up to 110 GHz. In addition, we investigate the effects of temperature variation on the thin film dielectric property. High-Q inductors were also designed on high-resistivity silicon and glass substrates.

In this paper, we have developed the evaluation results of low cure temperature (less than 200 deg C) dielectric materials in terms of process ability and adhesion on SiN and mold compound substrates. The results showed that the low cure temperature dielectric materials have good adhesion on SiN and mold compound substrate. Integration of thin film passives like inductors, capacitors and band pass filters are also demonstrated on this mold compound wafer platform using electroplated Cu and low cure temperature dielectric material. Developed thin film passives on mold compound wafer platform have significantly improved the passives performances that are benchmarked against high resistivity silicon wafer (HiRSi). Reliability test vehicles are fabricated using Cu RDL, low cure temperature dielectric material and electroplated Cu UBM with SAC solder bump interconnects. A complete description of dielectric material evaluation for EMWLP, process development of thin film passive fabrication and multi-layer RDL integration on reconstructed mold compound wafer has been discussed.

Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 mu m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10um. After plating, the micro bumps oil the Si chip are reflowed at 265 degrees C and the variation of bump height measured within a die is less than 5%. The under bump metallurgy (UBM) layer on the Si carrier used is electroless plated nickel and immersion gold (ENIG) with total thickness less than 5um. Assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.