Jan Hoentschel works for GLOBALFOUNDRIES as a Device Manager and is responsible for 28nm low power technologies. He manages an international device engineering team, which is handling several low power CMOS technologies starting from 40nm down to 28nm. Before he was working with Advanced Micro Devices and served several PD-SOI-CMOS device integrations from 130nm down to 32nm technologies for high performance microprocessors. In addition he was working within the product interaction and implementation group at AMD in Austin, TX. Jan Hoentschel is author and co-author of numerous technical papers and patents in the semiconductor field. He holds an MS and PhD in electrical engineering from the Technical University in Dresden as well as an MBA in General Management from the University of Applied Science Bielefeld. His research interests include HKMG, strain engineering, 3D FinFET device and technology concepts, lIIiV semiconductors and low power technologies on CMOS devices.

Continuous process-level and system-level innovation has driven Moore's Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.