A copper electroplating formula, composed of a single organic additive, nitrotetrazolium blue chloride monohydrate, is developed for the direct filling of the through holes (THs) of a printed circuit board (PCB) and the through-silicon holes (TSHs) of a wafer. Two plating modes, direct current (DC) and periodic pulse reverse (PPR) current, are employed to perform the filling plating. DC plating requires an extended time period and results in void formation at high current density. In contrast, PPR plating requires a shorter time and results in a very thin copper layer on the wafer surface after the TSH is fully filled. (c) 2013 The Electrochemical Society. All rights reserved.

Wafer testing in the semiconductor industry is generally performed using a multilayer probe card. In this paper, Castigliano's second theorem is used to derive analytical formulae for the contact force and scrub mark length generated during the probing test. The formulations are then integrated with a multiobjective programming algorithm to optimize the probe needle parameters in such a way as to ensure a uniform contact force and a minimum scrub mark length. The validity of the analytical model is confirmed by comparing the solutions obtained for the contact force and scrub mark length with the equivalent results obtained from finite element simulations. The effectiveness of the analytical model and optimization procedure is demonstrated by optimizing the needle parameters of a commercial four-layer probe card. It is shown that the optimized probe card not only produces a more uniform contact force than the original probe card but also yields a shorter and more uniform scrub mark length.

As the mobile and consumer devices continue to demand for more functionality and less power within a smaller dimension, integration of IC packages becomes essential for the successful introduction of electronic devices in the market. Stacked-die packages are finding increased usages in SiP (system-in-package) and PoP (package-on-package), while various new packages based on CoC (chip-on-chip) and TSV (through-silicon-via) technologies are being developed. To ensure the reliability of assembled parts, the dimensional stability of stacked-die packages has to been properly controlled. This is to ensure a predictable performance of interconnections can be achieved after SMT/PoP assembly and at various operating conditions. Especially, warpage characteristics caused by thermo-mechanical stresses need to be considered in product design. In this study, a systematic study of single-die, four-die and eight-die land-grid-array (LGA) package warpage characteristics was carried out using both Shadow Moire and Micro Moire techniques. Shadow Moire was used to study the package warpage in a temperature range from room temperature to 260°C to simulate the solder ball reflow conditions; while a Micro Moire instrument, with a resolution of 417 nm without phase shifting, was used to understand localized stress distribution within the package between room temperature and 104°C. Effects of die sizes, die thicknesses, number of die stacked, type of molding compounds and mold cavity heights can thus be correlated. When using single die packages as a control, Shadow Moire measurement results showed molding compound types have a greater impact on package warpage than die thicknesses and mold cavity heights. In an eight-die MCP package, larger die size exhibited higher warpage during thermal cycling, whereas under same conditions choice of molding compound is insignificance to achieve improved performance. It was also found when die sizes and mold cavity heights were kept the- - same, four-die packages with approximately 3 times the die thickness exhibited slightly less warpage than that of eight-die packages. However, of the two, eight-die package exhibited dimensional changes within a narrower temperature range under reflow conditions. Micro Moire measurement results clearly showed the stresses were concentrated at the die edges between adjacent stacked dice. These results are useful for employing new designs lead to better product reliability.

PurposeThe reliability of chip‐on‐film (COF) packages is fundamentally dependent upon the quality of the eutectic Au‐Sn joint formed between the Au bumps on the integrated circuit (IC) device and the Sn‐plated Cu inner leads. Therefore, it is essential that an appropriate bonding temperature is achieved during the inner lead bonding (ILB) process. The purpose of this paper is to identify the optimal processing conditions which maximize the reliability of the Au‐Sn joints.Design/methodology/approachThe paper commences by performing an experimental investigation to establish the temperature at three specific locations within the COF/ILB system in a typical gang‐bonding process. The relationship between the setting temperature of the bonding tool and the temperature of the tool surface is then calibrated using an off‐line experimental system. An ANSYS finite element (FE) model is then constructed to simulate the temperature distribution within the COF/ILB system under representative temperature conditions. The validity of the numerical model is confirmed by comparing the simulation results with the experimental temperature measurements. The FE model is then used in a 23 factorial design process to evaluate the effect of the principal COF/ILB processing parameters, namely the contact area, the tool temperature and the stage temperature, on the temperature induced at the interface between the Au bumps on the IC chip and the Sn‐coated Cu leads on the polyimide film.FindingsThe results reveal that the interfacial bonding temperature is determined primarily by the stage temperature.Originality/valueA regression analysis model is applied to the factorial design results to construct a COF/ILB design chart which enables the rapid identification of the stage and tool temperatures required to achieve the minimum feasible eutectic bonding temperature.

Wafers, wafer cassettes, and probe cards are critical assets for wafer testing houses. Any mistake will cause tremendous damage to wafer owners and to the testing houses. These assets shall be carefully stocked in stocking facilities such as stockers, nitrogen cabinets, trolleys, and testers with a reliable tracking system which can provide accurate and real-time inventory information. To register the individual locations of the assets, the most popular technology implemented today is the Barcode systems. Barcode is mature, stable, cost-effective, and widely implemented in various applications. However, Barcode is not fully automatic nor real-time, nor 100% accurate due to the possibility of human errors. A revolutionary technology of Radio Frequency Identification (RFID) is implemented to resolve these problems to achieve 100% accurate inventory information with real-time and automatic acquisition of asset locations.

Chip-On-Film (COF) packaging is an attractive solution for the direct attachment of chips onto a polyimide (PI) substrate patterned with copper leads. However, despite its many advantages, the eutectic Au-Sn alloy formed in the high temperature bonding process has a number of unsolved reliability issues. Accordingly, the current study performs a series of experiments to investigate the heat dissipation characteristics of the COF process in order to develop a design tool to predict the optimum eutectic bonding parameters. In the experiments, the temperature is measured at three separate positions on the inner lead bonding (ILB) apparatus using a thermocouple wire. The heat transfer characteristics of the bonding tool surface are also measured using a system comprising a PID controller, a solid state relay and a thermocouple extension wire. An finite element (FE) model is then constructed to simulate the temperature distribution within the COF/ILB system under equivalent temperature conditions. The validity FE model is used to construct a design chart which specifies the temperatures of the bonding tool and chip support stage which ensure that the Au-Sn eutectic temperature is achieved at the bump / inner lead interface. The results indicate that the tool temperature should be no lower than 100degC (with a stage temperature of 312degC) and no higher than 300degC (with a stage temperature of 302degC).

Redundant cells are added to a memory chip to replace defective cells during IC fabrication to increase overall wafer yields. Compared to other repairing methods, only a small chip area is needed to design laser fuses, moreover, just a few redundant rows or columns can significantly enhance the yields of memory wafers. The laser fuses are hence the most commonly implemented method to increase yields in both DRAM and SRAM IDMs. In conventional memory packages, either TSOP II or FBGA, the memory chips are probed and repaired first, then packaged, burn-in, and final test. Therefore, there is no issue in covering the laser windows on a memory chip after laser repairs since the laser windows are all encapsulated by molding compound. In flip chip technologies or wafer-level packaging, memory ICs are packaging in wafer forms instead of individual dies. Moreover, memory wafers are normally probed and repaired before packaging, therefore, the laser windows are also encapsulated by underfill materials or by molding compound. However, if the conventional chip probing, burn-in, and laser repair can be done after flip chip bumping or wafer-level packaging, the testing steps can be simplified, the testing cost can be greatly reduced, and more wafer yield can be gained. This study primarily focuses on the laser repair after flip chip bumping to explore the feasibility of laser repair through BCB passivation on top of laser fuses and to develop new processes to protect laser fuses during flip chip bumping. Three different conditions are studied, original laser windows with PI passivation opened, laser windows with BCB coated on the top of PI passivation, and laser windows with BCB coating without PI passivation. The laser windows with PI opened, the laser fuses can easily be “burned” with 1.0 μJ of laser energy and the die can successfully be repaired since a fuse is sublimated by the laser beam with its vapor exploded and broken through the covered dielectrics. There are two different thicknesses of coated BCB in laser windows, one is laser windows with BCB coated on the top of PI passivation and the other is laser windows with BCB coating without PI passivation where the thicknesses are 10.69 μm and 7.32 μm, respectively. The results of laser repair are almost identical. Even with the laser repair energy up to 1.8 μJ, the fuse can not be “burned” and its vapor can not explode and break through the dielectrics and the BCB on top, all the more, its vapor will go sidewards and cause cracks along the interfaces of BCB and the dielectrics, in the worst case, causing shorts between the adjacent fuses. From the results of the laser repair, it can easily be concluded that the fuse vapor cannot easily break through the dielectrics with a thick BCB on top, therefore, no further study on the parameters of laser repair through BCB is necessary. The laser repair should be performed without any BCB passivation nor any bumping residual inside the laser windows. Then, how to protect laser fuses inside the laser windows during flip chip bumping processes becomes very crucial. The protection of laser fuses can be done by using appropriate UBM materials during flip chip bumping processes, then after solder ball reflow, the UBM was removed by etching. It has been proven that the dielectrics on top of laser fuses will not be damaged during flip chip bumping processes.

Just in a few years, the data rates of DRAM memories have been running faster and faster, from 400MHz of DDR in the past, to 800MHz of DDR II now, and to 1600MHZ of DDR III in the near future. It is well known that TSOPII is the standard package for DDR and FBGA for DDR II defined by JEDEC standards. Moreover, there are various high-speed packages recently announced for DDR III such as FBGA and WLCSP through press releases. In 2007, there are great business opportunities lying ahead for DRAM packaging houses since the debut of Microsoft Vista where 512MB is the minimum memory requirement and 1GB recommended. However, if FBGA can not meet the requirements of high-speed applications such as DDR III and beyond, then all the investment of FBGA equipment in 2006 and 2007 will be a waste in the future. In this paper, both electrical characteristics of TSOPII and FBGA in high-speed applications have been studies by simulation and then confirmed by electrical measurement. 50ohm-load designed wafers at various operation frequencies were fabricated and assembled in TSOPII and FBGA using standard packaging processes. The maximum clock rates for TSOPII and FBGA with 50ohm-load designed dies can reach up to 0.34GHz and 2.0GHz which have been confirmed by both simulation and measurement results.