In this paper, two types of silver pastes with distinguishing particle size are incorporated to investigate the correlation of microstructure and physical properties of sintered materials. The one consists of the silver nanoparticles with an average size of 25 nm, while the other consists of the silver particles of $0.43 \mu \mathrm{m}$ and the flakes of $16.5 \mu \mathrm{m}$ in the micrometer scale. The morphology is observed with a field emission scanning electron microscope. The prepared disc-like samples own the diameter of 13.0 mm and the thickness of 3.0 mm, which satisfy the measurement requirement of thermal and electrical conductivities. Thermal conductivity is the multiplication of thermal diffusivity, specific heat and density. The laser flash method is used to measure the thermal diffusivity of at least three positions on this thin disc in the thickness direction bases on the temperature rise at the rear face of the thin-disc specimen resulting from an energy pulse on the front face. For electrical conductivity, both of the sintered samples were measured at the room temperature of about $23^{\circ}\mathrm{C}$ by a four-probe method. In addition, nanoindentation experiments were conducted on the prepared disc-like samples. The substrate effect can be negligible, as the penetration is less than the 0.1% of the thickness. By controlling the penetrating velocity of the Berkovich indenter, constant strain rates can be achieved. Upon the maximum penetration depth of 2000 nm, the indenter is held for 50 s to release the creep deformation. The corresponding creep strain rate are compared from the strain rate sensitivity point of view. In order to compare the plastic behaviour, the residual indentation are examined.
An optimized cascaded defect segmentation algorithm which combining with region growing and level set is proposed to segment effectively the joint defect in ultrasonic aluminum wire. Three algorithms, which include Log edge detection, neighborhood variance, and Gray-Level Co- occurrence Matrix (GLCM), to achieve the location of joint region. The redundancy region of Bonding joint is removed clearly, even there are much noise in the joint image. The modelling of region growing and level set are descried in detail, respectively. More, the defect segmentation implement is conducted in OpenCV, and the result proves that the cascaded defect segmentation combining with region growing and level set can effectively segment the defects of Bonding joints.
The purpose of this study is to verify the feasibility of Plastic Ball Grid Array (PBGA) under strong random vibration occurred in satellite during launch. Experiments were performed using large PBGA chips on polyimide PCB, which was installed to an aluminum frame. The tests were performed under two extreme random vibrations. The test results demonstrated the robustness of the PBGA packing structure enough to sustain the vibration loads. Numerical analyses were also performed and found that, unlike usual expectation, the natural frequencies higher than the first one and their modes in the power spectrum density frequency range could induce higher solder stress in the location other than the PCB center.
For the development of electronic packaging products, the mixture of micron-filler and nano-filler was adopted to improve the electronic property of conductive adhesive. The porpose of the addition of micron-filler and nano-filler is to achieve a higher conductive property, so that the perfect conductive adhesive could be obtained by the optimized conductive fillers. The conductive filler composed of Cu powders coated by nano-Ag layer and silver nanowire and resin matrix were mixed to fabricate conductive adhesive. The conductive filler composed of Cu powder coated by nano-Ag layer and silver nanowire could reduce the bulk resistivity and percolation threshold of conductive adhesive. When the conductive adhesive was cured at 170° for 60min using Cu powder coated by nano-Ag layer and silver nanowire as conductive filler and the content of filler was 60wt.%, the bulk resistivity of the newly formed conductive adhesive was low to $6.53\times 10- 5 \Omega \cdot$ cm, while the shear strength of the adhesive was 5.36MPa.
As electronic packaging is becoming thinner and lighter, it is necessary to address the grinding process issues in the silicon wafer. In this context, the self-rotating grinding method is usually employed to mitigate the backside grinding in thin wafers, due to its high effectiveness. However, as the residual stress cannot be completely eliminated from the grinding process, it will cause warpage and lead to die damage. This phenomenon has been investigated by applying the finite element method (FEM) when modeling the grinding process. In the present investigation, a simulation model of the grinding process was developed for analyzing the warpage process and the residual stress. To validate the simulation model, experimental testing was conducted, whereby Scanning Electron Microscope (SEM) was used to observe the wafer depth, and crystal lattice breakage was observed through Raman Analyzer. The experimental data were used to validate the simulation model of the grinding process, which was subsequently applied to analyze the warpage and the residual stress in the wafer grinding.
A through-silicon-via (TSV) underfill dispensing method was introduced in previous studies to fill the under-chip space of a 2. 5D die/interpose package. A jet dispensing valve was used to dispense free droplets of an underfill fluid into a central TSV. The TSV functioned as an inlet for fluid flow and a fluid reservoir to uninterruptedly supply the underfill fluid. In an underfill process, the time required for completely filling the under-chip space is so-called “filling time As the underfill fluid commonly flows very slow, shortening the filling time in underfill process is substantial to reduce overall processing time. This study analyzes the fluid flow behavior in the under-chip space and investigates the effect of material properties and bump parameters on filling time.
The window glass substrates have been generally used in optical semiconductor and micro-electrical-mechanical system packages. The determination of bending strength of such glass substrates is essential for ensuring good yield rate and reliability of those packages. For evaluating the dicing effect on the bending strength of window glass substrate, the typical 3PB test is adopted in this study. One of paradoxes is that the test specimens are generally plate-like, rather than beam-like, but a beam stress theory is commonly used for calculating strength from experimentally obtained maximum load in the 3PB test. Therefore, the other goal of this study is to determine the free-edge stress of the test specimen using finite element analysis during the 3PB test, if failure initiation of the test specimen starts at the free edge. The test results will be presented in terms of bending strength for edge (frontside) control and non-edge (backside) control cases, associated the failure modes. And precise edge-stress calculation will be discussed in detailed through finite element analysis with various models, including non-contact and contact models with both displacement and force boundary conditions.
Fan-out Wafer-level Packaging (FOWLP) technology has become one of the most rapid packaging technologies which can meet consumer demand for electronic devices. Since there are many advantages to FOWLP, several important issues remain to be addressed, including yield, reliability, thermal performance, die shift, and warpage. Therefore, the main reasons that cause the yield problem of the FOWLP are the mismatch of temperature loading and coefficient of thermal expansion(CTE) among the components of the package, and the other reason is the chemical shrinkage of liquid type epoxy molding compound during the cure process. In this study, the main goal is to assess the process-induced warpage of FOWLP during the fabrication process. To predict the amount of warpage precisely, a process-dependent simulation model which includes the cure-induced shrinkage of the liquid type of molding compound obtained by measurement is proposed. To confirm the validity of the simulation model, the simulation results are compared to the online warpage measurement data. Finally, the influence of the material properties of molding compound parameters on the process-induced warpage is discussed.
Accompanying the rapid progress of the digital network information and spread of mobile devices, there is strong demand for the high functionality and miniaturization of devices. Thus, the chip ultra-thinning and stacking technologies are important to achieve it. DBG (dicing before grinding) process is popular thinning process for ultra-thin chip. But, dicing wafers always causes chip side and surface chipping. This defect on chip faces become source of chip-cracks. SDBG (stealth dicing before grinding) process is a novel process known as SD (stealth dicing) offers a potential defect-free singulation process. But, SDBG process often causes chip-cracks because of very narrow kerf by SD. Chip-crack is caused by collision of chips by chip-shift in the manufacturing process. Therefore, BG (back grinding) tape for SDBG process required for controlling chip-shift. Especially, key process for controlling chip-shift is back grinding process. In order to control the chip-shift, 1st key point is Young’s modulus of base film. Elongation of BG tape in laminating process causes chip-shift, so we have optimized base film which can be control chip-shift. The 2nd key point is elastic modulus and thicness of adhesive layer. We have studied the elastic modulus and thickness of adhesive layer which can fill to wafer pattern and control chip-shift.
Recently, all the electrical device frequency becomes higher and higher in order to enable electronic products have better performance and become much faster such as CPUs, cellphones, smart watches...etc. Almost all the products you can see around yourself contains electronic circuit. With generations of Internet of things(IOT) coming, electronic products will everywhere in our lives in the near future. It also means that the circuit in integrated circuit (IC) and printed circuit board (PCB) must become shorter and shorter. With the size of PCB and IC shrinking, measurement in near field system becomes more and more difficult due to the limitation of the magnetic probe resolution. Thus, we reduce the width of the probe and build the model in ANSYS HFSS to see the resolution. (Fig.1. is our simulation structure in ANSYS HFSS) However, according to Faraday's law, with the area of sensitive loop reducing, the induced electromotive force must be decreased. In a near field measurement system, we usually connect a low noise amplifier (LNA) on the top of the magnetic probe, and the inductance signal of the probe must to be large enough (At least greater than the dynamic range of the LNA) for a LNA to be recognized. All in all, we have to find the balance between resolution and inductance.
A lot of high power LED products adopt remote phosphor instead of conformal phosphor, since remote phosphor design can increase the light output and decrease the manufacture cost. However, whether the new design will affect the thermal performance is still not very clear. Thus, this paper is focus on the thermal performance of high power LED systems. The numerical models are built based on the real products and the parametric studies are also implemented. From the simulation results, it is found that the average temperature on remote phosphor layer is 10% lower than on conformal phosphor layer. This is helpful for the LED systems’ life since phosphor aging is slower under lower working temperature. The parametric studies show that the heat sink area doubles brings the temperature 10% off for total system.
Modern electronics are seriously limited by heat dissipation. Interfacial thermal resistance and constructing thermal conductive network are found to be the key issues. In this work, pine needle-derived carbon (PNDC) was prepared by a simple carbonization method. At optimized condition 50°C for 2 hrs, it shows impressive thermal conductive property. Importantly, the systematic structural characterization indicates that this derived carbon itself has well aligned, interconnected network-like, and channel-shaped microstructure which benefits the interface contact. The resulting Ag @PNDC/epoxy composite films were fabricated via a vacuum infiltration technology, the results show a much enhanced heat transportation $(0.537 mathrm{Wm}^{-1} \mathrm{K}^{-1})$ as compared to that of pure epoxy resin $(0.187 mathrm{Wm}^{-1} \mathrm{K}^{-1})$.
Micro-Electro-Mechanical systems based structures offer a reliable platform for investigating properties of thin metal film which are strongly influenced by the deposition process as well as post processing conditions during the wafer processing. The present work introduces a methodology to fabricate free standing structures based on silicon on Insulator (SOI) technology, which offers a tool to study material properties of silicon-thin metal interface under different conditions. A variety of micro structures such as straight/curved cantilevers, beams, as well as plus sign and theta specimens of varying dimensions have been fabricated. Different micro structures of silicon having thisckness of 2.8-3$\mu\mathrm{m}$ were deposited with copper films of 1000-3000 nm thicknesses. Among them, cantilevers of different dimensions have been used to study the varying grain size of copper from submicron to micrometer range. By using the nanoindentation technique, the stiffness and modulus of elasticity measurements were carried out for pure silicon cantilevers of varying width and Si-Cu compsite cantilvers of varying copper thicknesses with different grain size. This methodology of fabrication offers flexibility to characterize different kinds of thin films of various dimensions and study the impact of individual process conditions on properties of thin films.
This paper presents a dual-band dual-polarization stacked dielectric resonator antenna (DRA) element design. Two mutually perpendicular bonding wire structures are used for realizing wide bandwidth feeding network. The DRA is implemented in low-cost integrated passive device (IPD) envirnoment. This millimeter wave DRA exhibits wide bandwidth, wide beamwidth and high gain characteristics. It is suitable for dual polarized millimeter wave scanning antenna array system application.
Detection of light in the near- and short-wave infrared spectral region is of great interest for applications ranging from imaging to sensing. However, silicon commonly employed for photodetectors is limited in its spectral range to wavelengths of 400… 1100nm due to its band gap of $\sim$1.1eV. Materials for light detection in the wavelength range $\gt1100$ nm are typically III-V-based semiconductors such as e.g. InGaAs which are difficult to integrate with CMOS technology, hindering use in main-stream applications due to technical issues and associated high cost. Here, we present graphene-silicon hybrid structure photodetectors which demonstrate an extended spectral detection range from $\sim$400… 1700nm.
High performance dielectric storage films are widely applicated in the high technology field like new energy vehicles, wind turbine generators, avionic industries, oil and gas explorations etc. To improve the energy storage density of the dielectric films, achieving high electric breakdown strength and permittivity are required. In this study, we designed a hybrid that the graphene quantum dots are deposited on the surface of BaTiO 3 particles (denoted as BT@GQDs) as fillers in the PVDF films. The results show that the GQDs has the function of enhancing the polarization of the composites. Higher permittivity and displacement of the BT@GQDs/PVDF composites were observed than that of the BT/PVDF composites. Meanwhile, high electric breakdown strength was achieved for the BT@GQDs/PVDF composites. Hence, the energy storage density of the composites was significantly improved. A high energy storage density of 13.6 J/cm 3 , which is 197% of the pure PVDF films, was obtained for the BT@GQDs/PVDF composites filled with 3 wt% BT@GQDs.
The rapid development of electronic devices that has occurred in recent years has prompted the demand for greater functionality in consumer electronics, with a particular emphasis on multifunctionality, miniaturization, and weight reduction. These restrictions have rendered the design of microelectronic structures much more complex and challenging, since the semiconductor technology has remained relatively unchanged. Recently, high bandwidth package on package (HBPoP) was introduced as a potential candidate for the processor that can be incorporated into smartphones, tablets, and other consumer electronics. Its key advantage stems from high-bandwidth and high-performance computing. However, as the warpage performance of the package is a key factor in the package assembly, it must be investigated before HBPoP can be adopted in practice. The warpage of package on package (PoP) is induced by the mismatch between the thermal expansion coefficients that arises in the reflow process. Once package warpage occurs, it may cause delamination within the structure, as well as induce package assembly failure. Thus, it is a significant reliability issue. In order to improve the PoP warpage performance, a prediction model is developed as a part of the present study by combing the experimental testing results with simulation results. The main objective is to provide the guidelines for optimizing the PoP structure with the goal of improving the warpage performance.
Mechanical robustness of polymer solar cells should be ensured for the device reliability, but the brittle active layers of fullerene derivative based polymer solar cells would fracture easily causing the device failure. Therefore, mechanical properties of polymer solar cells should be investigated thoroughly in order to enhance the mechanical reliability. Herein, the mechanical properties of polymer solar cells were examined depending on the acceptor types (polymer or small molecule acceptors) and the content. In addition, the fracture behaviors were revealed in detail with various morphology analyses. This result demonstrates the importance of polymer acceptors to improve the mechanically robustness of polymer solar cells.
Metal organic framework (MOF) has recently attracted much attention due to its uniform pores consiting of metal ions and organic ligands. MOF was conventionally produced by a liquid phase method such as a hydrothermal way, but gas-solid phase reaction to form MOF on a substrate using ligand gas was recently reported by Ivo et al. However, orientation controlled MOF film is not yet obtained by gas-solid reaction. In this study, we investigated oriented MOF growth with highly oriented Al:ZnO (AZO) sputtered on single crytalline Al 2 O 3 (0001) substrates through solid, liquid, and gas-solid phase reaction. The crystallographic structure by XRD exhibited ZIF-8 film was polycrystalline.
Owing to the fact that the requirements of the lifestyle for electronics devices has been shifted to a stage physically small and thin, a high density of chips is designed to meet the foregoing demands under the limited space. Although in plane IC packaging technology has been maturely developed, it has encountered a bottleneck which stops it from immediate progress. Therefore, it is inevitable that the 3D-ICs packaging becomes the major goal of technological developments in the future. Among them, through silicon via (TSV) is one of the critical techniques. Because of the complexity in the design of 3D-ICs, the interaction among packaging components is expected to affect the reliability. Consequently, this research presents the 3D-ICs packaging with two ultra-thin chip stackings to examine their mechanical reliability of TSV and SnAg microjoints under only the thermal cycling test and the accompanied effect of process-dependent thermal loading simulation combined with the introduction of temperature cycling loads. Several concerned parameters of the above-mentioned packaging framework, such as the chip thickness, TSV pitch, and TSV radius, are parametrically discussed by finite element analysis while the filled underfill materials with different Young's modulus are taken into account. separately. The analytic results show that when the double-layered chip stacking packaging structure is applied by the thermal cycling period, a better fatigue life of SnAg microjoints could be obtained under the situation of either the thinner chip, the longer TSV pitch, or the smaller TSV radius. Finally, through the analytic assistance of a full factorial design, the geometrical effects of double-layered chip stacking packaging are performed parametrically investigations.
