The performance, size, weight and power requirements for future systems are increasingly demanding. These can be met by intimate integration of lower power and higher performance scaled CMOS and compound semiconductor technologies into smaller areas and volumes. The more adaptable and more intimate is this integration between two or more technologies, the more flexibility is given to the designer for the selection of the technology for a specific function, or even better, for an optimum combination of different transistor technologies in the same function or cell in the design. Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing integration processes, design kits and thermal simulation tools to integrate submicron CMOS, InP HBT, GaN HEMT and high-Q passive technologies for advanced DoD systems. We have demonstrated integration of NGAS' InP HBT and GaN HEMT technologies on 65nm and 45nm CMOS wafers.

Under the Compound Semiconductor Materials on Silicon (COSMOS) DARPA program, Northrop Grumman Aerospace Systems (NGAS) has developed an advanced heterogeneous integration technology to intimately integrate compound semiconductor (CS) devices and circuits on CMOS/SiGeBiCMOS wafers. The integration approach is based on a direct face-to-face bonding between pre-fabricated InP chiplets and Si wafers. The heterogeneous integration process is compatible with any semiconductor technology. This integration enables significant improvement in dynamic range and bandwidth of high performance mixed signal circuits. In this paper we describe the integration approach and present two demonstration circuits.

A 5-layer and 97 GHz (W-band) single element vertical transmit (Tx) integrated circuit is demonstrated that incorporates a 4-stage Gain and Power amplifier, 4bit phase shifter, and 4-bit serial to parallel digital controller, within an ultra compact 1.28 mm volume (1.6 x 1.6 x 0.5 mm). The multilayer Tx integrated circuit demonstrates >10 dB gain, with >12 dB input and output return loss. For the first time, a compact and heterogeneously integrated three-dimensional (3D) multilayer module is demonstrated with unprecedented millimeter-wave functional density. The attainment of this technology is anticipated to result in enormous improvement of size, weight, performance, and cost of future military systems that operate at millimeter-wave frequencies.

Double crystal X‐ray diffraction imaging and a variable temperature stage are employed to determine the stress distribution in heterogeneous wafer bonded layers though the superposition of images produced at different rocking curve angles. The stress distribution in InP layers transferred to a silicon substrate at room temperature exhibits an anticlastic deformation, with different regions of the wafer experiencing different signs of curvature. Measurements at elevated temperatures (≤125 °C) reveals that differences in thermal expansion coefficients dominate the stress and that interfacial particulates introduce very high local stress gradients that increase with increased temperature. For thinned GaAs substrates (100 μm) bonded using patterned metal interlayers to a separate GaAs substrate at ≈200 °C, residual stresses are produced at room temperature due to local stress points from metallization contacts and vias and the complex stress patterns can be observed using the diffraction imaging technique. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

In0.86Al0.14As/In0.86Ga0.14 As double heterojunction bipolar transistors (DHBTs) were grown on InP substrates by using sub-micron 6.0 Aring metamorphic graded buffer layers. Good DC and RF characteristics have been demonstrated with a current gain of 30, low base-collector reverse leakage (<muA), low turn-on voltage (0.45 eV), practical breakdown voltage (~2.5 V), and peak frequencies fT and fMAX exceeding 150 GHz. Functional circuits with complexity ranging from 20 to 1100 devices have been successfully demonstrated with power dissipation reduced by a factor of two compared to equivalent circuits designed with conventional InP technology

Hydrogen-exfoliation has become a viable approach to transfer SiC thin layers onto different substrate materials. However, little attention has been paid to the exfoliation-inducing annealing conditions. To investigate the annealing conditions, 4H SiC wafers were implanted with either 2.5×1016 H2 + cm-2 or 5.0×1016 cm-2at 37 KeV. Post-implant, multi-step annealing sequences were examined in order to promote more efficient blistering, and it was found that a low temperature initial annealing step (T ≈ 500°C) can decrease the annealing time necessary in the high temperature regime; this was attributed to a nucleation of hydrogen induced platelet defects during the low temperature annealing regime and efficient splitting during a higher temperature (900 °C) anneal. This process is similar to what is observed for InP and Si exfoliation, except that the annealing processes occur at higher temperature.

Equations governing scans along arbitrary directions in reciprocal space were developed and used to map reciprocal lattice points (RLPs) with radial raster patterns to study mosaic structure in GaN thin films deposited on semi-insulating 4H-SiC substrates using AlN nucleation layers (NLs). The films were grown by molecular beam epitaxy, keeping the GaN growth conditions the same, but using different AlN NL growth conditions. Mosaic tilt angles determined from symmetric RLP breadth measurements were similar for all samples measured, consistent with screw and mixed dislocation densities determined from transmission electron microscopy (TEM) measurements. Mosaic twist was determined using off-axis skew-symmetric high resolution x-ray diffraction measurements of asymmetric RLP breadths, yielding results consistent with grazing incidence in-plane x-ray diffraction twist measurements. A clear correlation between the twist angle and the edge and mixed dislocation densities determined by TEM was not observed, warranting careful consideration of dislocation structure.

Exfoliation by hydrogen implantation of GaN grown on sapphire was successfully accomplished for the purpose of wafer bonding and layer transfer. Hydrogen ions were implanted at 60 keV, with low doses of 2.5 and 5.0x10(16) H-2(+)/cm(2). High resolution x-ray diffraction and cross-sectional transmission electron microscopy were used to investigate splitting kinetics. High temperature exfoliation (>400 degreesC) was determined to depend on the diffusion of hydrogen. Low temperature exfoliation (<400 degreesC) was found to be limited by the crystallinity of the GaN. Extremely defective GaN layers were unable to be exfoliated in this lower temperature regime which was attributed to hydrogen trapping from a high density of dislocations.

The application of X-ray scattering techniques to InP and InAs substrates is presented. Applications focus on double crystal X-ray topography (imaging) and reciprocal space scans. Both types of substrates have shown dramatic improvements in crystalline quality and wafer size over the past few years. The topographic measurements display large area images of variations in both lattice dilations (strain) and lattice tilts. Low angle boundaries, precipitates, and dislocations are readily imaged over the entire wafer. Images taken at different rocking curve positions provide information about crystallographic defects and "rocking topographs" provide quantitative information about long range deformation in the substrates. The reciprocal space scans presented here demonstrate the sensitivity of triple axis rocking curves to subsurface damage in both InP and InAs.

X-ray topography or diffraction imaging comprises a family of techniques employed to study semiconductor materials. This study assesses and compares three variants of diffraction imaging: double crystal x-ray topography, Lang x-ray topography, and a new technique known as Bedescan(TM) applied to alpha-SiC substrates and wurtzite GaN heteroepitaxial layers.

We discuss the interpretation of images of /spl alpha/-SiC substrates and GaN layers deposited on SiC using two common variants of diffraction imaging: double crystal (reflection) topography and Lang (transmission) topography. Dependence of image resolution on layer rocking curve breadth is demonstrated, and implication for limitations imposed by thin and defective layers are discussed.

In this paper, the successful exfoliation of 200 nm GaN layers grown on sapphire substrates was achieved usiing H2+ implantation and subsequent annealing. We demonstrate that the extent of exfoliation depends not only on the implant dose, but also on the crystallinity of the GaN layer. Extended defects are not uniformally distributed over the wafer, so certain areas showed much more pronounced exfoliation than other areas.

We studied the propagation and interaction of individual misfit dislocations in strained p/p+ Si wafers. Relaxation of misfit strain occurs at the wafer edge during high-temperature epitaxial growth. The thick epitaxial layer (about five times the critical thickness) and low misfit dislocation densities (~100 cm-1) are highly compatible with a non-destructive study via x-ray topography. We determined that as a gliding 60° misfit dislocation encounters a strain field in its path, it cross-slips to a specific lattice direction. Misfit dislocation segments with either an orthogonal or quasi-parallel (in the case of the off-oriented substrate) glide direction of the Burger's vector were determined to act as cross-slip initiation sites. This interaction happens during layer growth as well as post-growth annealing cycles. We did not find a case of misfit dislocation blocking during sample annealing. No occurrence of annihilation or multiplication reaction of crossing dislocations was detected during our studies. We show that, due to geometry, a distribution of tilt across the wafer surface results from preferential cross-slipping events. Our results are applicable to early stages of strain relaxation in other strained systems, like graded buffer layers.