The impact on doping profile, surface roughness and defect production of each process step for a suggested Multiple epitaxy and implantation (MEI) process for Super-junction has been investigated through Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. Results show that the suggested process can possibly reduce the cost of the original fabrication and speed up the process.

This work reports the first demonstration of monolithic integration of a 20-V CMOS gate driver with a 1.7-kV JBSD-embedded VDMOSFET (JBSFET) on 4H-SiC. Device-level isolation between low-voltage CMOS circuits and high-voltage power MOSFETs is achieved using a high-energy implanted p-bottom layer. A LOCal Oxidation of SiC (LOCOSiC) isolation scheme is adopted to mitigate surface topography and facilitate a double-metal interconnect process. Benefiting from an optimized doping profile and a recessed source contact, the VDMOSFET exhibits an ultra-low specific on-resistance of 2.96 mΩꞏcm2. The embedded JBSD, formed by wet etching and Ar plasma treatment, achieves a low Schottky barrier height of 1.23 eV with excellent uniformity and weak temperature dependence. While the embedded SBD slightly increases on-state resistance (Ron), it significantly reduces gate charge (Qg), leading to a 5% improvement in the RonꞏQg figure of merit. Finally, reliable operation of the integrated 1.7-kV JBSFET driven by the on-chip CMOS gate driver is experimentally demonstrated.

In this work, we demonstrate the crystal-face-resolved gate switching instability in 4H-SiC UMOSFET. By employing a source-separated single-cell (SSSC) structure, we are able to characterize GSI of each crystal face and revealing reliability discrepancies arising from variations in crystal orientation, interface quality, and process-induced sidewall asymmetry.

This paper presents a thick corner oxide (TCOX) located at the trench bottom of a 1.7 kV SiC trench UMOSFET and a monolithically integrated 20 V Tri-Gate SiC CMOS circuit to realize smart control and high-power IC applications for the first time. This integration provides a solution for simultaneously embedding Tri-Gate FET based complementary metal-oxide-semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. Trench MOSFETs are key to achieving lower specific on-state resistance (Ron,sp) by enabling further scaling of power devices. Among CMOS technologies, FinFET CMOS has been used to further enhance performance due to its well-behaved short-channel effects (SCE) and its ability to overcome device scaling issues. In this work, we successfully demonstrated a process for integrating a 20 V SiC Tri-Gate FET CMOS into a 1.7 kV trench UMOSFET with a TCOX structure. The threshold voltage (Vth) of the Tri-Gate FETs is 1~2 V lower than that of the planar MOSFETs, which enhances circuit speed and reduces power consumption. The Ron,sp of the fabricated UMOSFET can be reduced to 3.5 mΩ-cm2, accompanied by a similar density of interface states (Dit) at both the mesa and trench side wall regions. A variety of Tri-Gate FETs based CMOS circuits were designed and their functions verified on this platform, enabling the realization of smart power IC management.

Silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) technology and its circuit applications have been rapidly advancing, making the stability and reliability of planar p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) increasingly important. In this study, a channel-length-dependent threshold voltage instability was observed under both gate bias stress and gamma-ray irradiation. The results indicate that the majority of positive charge trapping originates from hole injection induced by external bias. Secondary ion mass spectrometry (SIMS) analysis confirmed the retention of aluminum species in the gate dielectric after thermal oxidation. Based on these experimental findings, a dopant diffusion model was proposed, suggesting that dopant contamination in the gate oxide is the primary cause of the channel-length-dependent instability.

This study investigates the electrical characteristics and instability of 4H-SiC NMOSFETs with varying channel lengths. A phosphorus-doping model in the gate oxide is proposed to explain the observed phenomenon. The incorporation of implanted dopants into the thermal oxide was first confirmed through SIMS analysis, followed by TCAD simulations that verified their lateral diffusion at high temperatures. In short-channel NMOSFETs, the entire gate oxide contains a high density of phosphorus, which introduces a high concentration of electron and hole traps. As the channel length increases, the proportion of the P-doped region decreases, leading to improved oxide quality. This phosphorus-doping effect should be considered when evaluating the reliability of short-channel MOSFETs.

MOS devices interface defect density measurements such as the hi-lo CV method and the conductance method are extremely important and widely used. Interface defect response time is a key parameter in both measurements as well as in their interpretations. It is widely accepted that interface defects at energies close to the band edge have too short a response time to be measured properly by these techniques, unless very high measurement frequencies are employed, which greatly increases the experimental difficulty. Consequently, near band edge interface defects are deemed unreliable and generally not reported. Here we show that the time constant of band edge defects has been misunderstood. Specifically, we show that as the capacitor is biased into accumulation - a necessity to measure defect levels near the band edge, the defect response time levels off instead of continuing to decrease. As a result, the commonly available 1MHz measurement frequency is more than adequate even for defects near the band edge.

We successfully fabricated a 1.7 kV-class 4H-SiC VDMOSFET monolithically integrated with a 20 V inverter-chain gate driver (GD) featuring P-bottom isolation (PISO) and a recess contact structure. The DC and AC switching characteristics of the gate driver were demonstrated at a minimum working voltage of 12 V and a maximum undistorted working frequency of 200 kHz. The 1.7 kV VDMOS exhibited an on-state specific resistance (Ron,sp) of 3.23 mΩ-cm2 and a breakdown voltage (BV) of 1917 V. Finally, the high-temperature response of the integrated GD and VDMOS was also demonstrated up to 200°C. Therefore, we believe the integrated SiC GD+VDMOS can be effectively utilized in power modules to offer a smaller form factor and higher power efficiency compared to conventional solutions using a discrete Si packaged IC.

The cause of low mobility in SiC MOSFETs, particularly after post-oxidation nitric oxide (NO) annealing, remains a critical question in wide-bandgap device reliability. Previous reports have attributed poor mobility to the formation of fast near-interface traps (NITs) introduced by NO annealing. In this study, we utilize fast drain current-gate voltage (I-d-V-g) measurements, which has a simple interpretation, to directly probe these NITs to check if these assertions are true. Our fast drain current-gate voltage measurements show that on the time scales of 10 ns to 500 ns, filling near interface traps leads to <10 % reduction in the mobility, implying that such traps cannot explain the poor mobility in SiC MOSFETs. This finding challenges the attribution of poor mobility solely to fast NITs and point toward alternative mechanisms, such as above band edge states.

A novel Separated Source Electrodes Kelvin (SSEK) structure is proposed to effectively eliminate most of the series resistance in a VDMOSFET, enabling accurate channel mobility extraction. By utilizing the SSEK structure, we can separately measure the resistance of the left and right channels, thereby achieving more precise channel mobility extraction and effectively evaluating process improvements for vertical power MOSFETs.

High-performance 4H-SiC CMOS devices were fabricated using a self-aligned counter-doping process during the $\mathbf{P}$-well formation. LOCal Oxidation of SiC (LOCOSiC) isolation is essential for this technology. Both NMOSFET and PMOSFET exhibit low leakage current and high conduction current. The CMOS inverter demonstrated a symmetric voltage transfer curve, along with high noise margin high, noise margin low, and corresponding voltage gain.

In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and 1700-V VDMOSFET devices on a single 4H-SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reach-through in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV, was then conducted to verify the breakdown voltage (VBD) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (VBD) exceeding 2000 V.

This article evaluates four methods for extracting channel mobility using source-separated single cell (SSSC) structure: parallel, series, hybrid, and separated source electrode Kelvin (SSEK). These methods are applied to UMOSFET for direct channel mobility extraction. The first two methods can not eliminate the influence of the resistance at the drain side, and the measured mobility is a mixed result of the left and right channels. The measurement and extraction procedure of the Hybrid method is more complex. Among these methods, SSEK is the simplest and allows for the analysis of the left and right channel characteristics. The channel of the UMOSFET closest to the accurate a-face exhibits lower threshold voltage, higher field-effect mobility, and lower temperature dependence. These characteristics are believed to result from fewer SiO2/silicon carbide (SiC) interface traps.

Each server rack within the data center necessitates a Power Supply Unit (PSU) to facilitate power delivery. The PSU is designed as a combination of a Power Factor Correction (PFC) converter and a half-bridge LLC resonant converter, specifically employed at the front end of AI servers to convert 110 V AC to 48 V DC. This study focuses on the comparative analysis of different power devices utilized as switching components. In particular, the effects of Silicon (Si), Silicon Carbide (SiC), and Gallium Nitride (GaN) on power factor and efficiency are investigated. The findings aim to provide insights into the optimal selection of power devices for enhancing the performance of power supply circuits in AI server applications.

The impact of silicon nitride (Si₃N₄) stress on 4H-SiC has been investigated. Current-voltage (I-V) measurements on Schottky barrier diode show that Si₃N₄ films thicker than 100 nm degrade both the ideality factor and Schottky barrier height. A 45-nm sacrificial oxidation effectively reduces defects from a 100-nm-thick Si₃N₄ layer, but defects persist with films over 300 nm. Interface state density of metal oxide semiconductor capacitor with a 44-nm-thick gate oxide confirms the effectiveness of sacrificial oxidation in mitigating defects.

The impact of gamma ray irradiation on the blocking characteristics of edge termination on 4H-SiC has been investigated. The dominant mechanism for the degradation of breakdown voltage (VBD) is the trapping of net positive charges in the field oxide (FOX), while the increase in interface state density can be ignored. Through measurements of FOX MOSFETs and edge termination test structures, we found that edge termination with LOCal Oxidation of SiC (LOCOSiC) FOX exhibits lower variation in VBD compared to conventional CVD FOX. Furthermore, it shows almost no susceptibility to gamma-ray irradiation up to 250 kGy. Therefore, it is recommended to utilize LOCOSiC FOX to mitigate the impact of irradiation on the blocking characteristics of SiC power devices’ edge termination.

The radiation hardness of 4H-SiC MOSFETs with LOCal Oxidation of SiC (LOCOSiC) isolation structures is evaluated in this work. NMOSFETs and PMOSFETs utilizing a 40-nm-thick thin oxide and a 200-nm-thick Field Oxide (FOX) as the gate oxide were fabricated and subsequently exposed to gamma-ray irradiation. In comparison to conventional Chemical Vapor Deposited (CVD) FOX, the LOCOSiC-isolated thin oxide MOSFETs exhibit a similar degree and trend of degradation after gamma-ray exposure. Regarding the FOX MOSFET, the positively trapped oxide charge in the FOX generated by irradiation leads to a decrease in the threshold voltage of the CVD FOX MOSFET. Conversely, the defect layer beneath the LOCOSiC FOX pins the surface potential, enabling the LOCOSiC FOX MOSFET to remain in the turn-off state even when the irradiation dose reaches 100 kGy and the gate bias increases to 24 V. These findings suggest that LOCOSiC isolation possesses exceptional radiation hardness and holds potential for application in SiC devices operating in strong radiation environments.

Etching active area by dry etching method can precisely control the length and width of the devices, but it may damage the SiC surface. In this paper, we fabricated metal-oxide-semiconductor capacitors (MOSC) using different etching methods to compare the effect of etching methods on the SiO 2 /SiC interface and dielectric breakdown. It is observed that dry etching will degrade the surface roughness of SiC and the interface state density at the SiO 2 /SiC interface. Post-oxidation NO annealing cannot passivate the interface effectively. The breakdown field of gate oxide on the dry etched sample is also degraded. These results indicate that dry etching of SiC surface should be avoided when fabricating MOS devices.

In this study, a novel self-aligned process is proposed to reduce the specific channel resistance, and the electrical characteristics affected by process variation are also verified through TCAD simulation. Also, when compared to other self-aligned processes, the process introduced in this paper offers the advantages of stable electrical characteristics and lower process costs.