In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, address decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.

Conventionally, the access failures in SRAMs are treated at core cell level by means of differential bit line voltage analysis. In this work it is shown that under the assumption of random process variability, the conventional approach no longer suffices. It still holds that the differential bit line voltage is degraded by the variability in core cell transistors, but the way this voltage difference is interpreted by the sense amplifier to complete the read operation is influenced by random variability affecting its transistors. Case studies show how variability affecting the sense amplifier can degrade or improve its ability to read the data stored by the core cell, which is itself affected by variability. Using principal component analysis and the SB-SI method, we performed a parametric analysis of the sense amplifier/core cell system and we evaluated the joint probability of access failure. A three times increase in the failure probability has been observed when compared to cell's failure probability. Also, the minimum variability value for which a failure is observed is ~2.5X smaller when joint variability is assumed compared to the case when only the core cell is affected by variability.

Voltage regulation systems offer an efficient mechanism for reducing static power consumption of SRAMs. When the SRAM is not accessed for a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cell array as low as possible without data loss. Therefore, reliable operation of such device must be ensured by using adequate test techniques. In this work, we propose low area overhead built-in self-test (BIST) and built-in self-repair (BISR) schemes that can be embedded on the SRAM to automatically test and repair the voltage regulator. Simulation results prove the effectiveness of the proposed technique for detecting, diagnosing and repairing voltage regulators of low-power SRAMs.

Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and dynamic faults due to resistive-open defects in the SRAM core-cell, taking into account the effects of random process variability in core-cells and IO circuitry. Statistical analyses have been performed to evaluate the SRAM failure probabilities accounting for defects at each possible location. The results show that random process variability in the SRAM core-cell and IO circuitry have an important effect on the behavior of an SRAM array and also on the defect coverage of various commonly-used test sequences. It is shown that under variability, the minimum defect size detected with maximum probability is more than 2X larger than the minimum size detected in nominal conditions, thus leaving a large range of defects undetected. Several stress conditions during test have been evaluated to assess their capability to increase the defect coverage under random process variability.

Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.

SRAM testing is becoming more and more challenging due to issues caused by continuous device scaling. Fabricated SRAMs are submitted to random and systematic process variability, which strongly affect the cell's behavior and also the ability of test algorithms to detect faults. Traditionally, bias conditions have been used to improve the behavior of the SRAM under process variations by applying body bias to compensate for the effect of variability. Based on the same principle, bias conditions also affect the cell's behavior when resistive-opens are present, hence affecting test's defect coverage capability. Both body- and source-bias conditions are analyzed in this paper to find the way to improve defect detect ability in the SRAM cell. Source-biasing has been proven to be the more effective of the two, leading to more than 3X improvement of the defect detected value. Also, by adapting the source-bias conditions to process parameter values, over- and under-testing of the SRAM can be avoided.

Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.

We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90 nm, 65 nm and 40 nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes.

Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. Finally, we propose an efficient test solution targeting the set of identified fault models.

A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

This paper proposes an innovative approach to cope with defects in SRAM bit-cell array. Traditional approaches use spare parts (rows, columns or blocks) to replace defective bit-cells. Instead of replacing defective bit-cells, we propose to operate the SRAM with reduced storage capacity whenever defective bit-cells are present. We implement this feature through a programmable combinational logic, called Scrambling Module (SM), which scrambles the memory addresses. The scrambling changes the addresses of the defective bit-cells, grouping them in an idle address zone located at the end of the memory address plan. The SM is described by using a mathematical formulation based on linear algebra. The proposed technique can be used in combination with traditional redundancy approaches using spare rows and/or columns. The effectiveness of three different SM is demonstrated, considering a 1MBit SRAM. For a given level of defect tolerance, it is shown that our technique can reduce the amount of spare area by several orders of magnitude. Moreover, as the SM is implemented as an external block, it does not affect the maximum operation frequency of the SRAM. Instead, it affects the memory access delay.

Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.

In this paper, we present a study on the effects of resistive-bridging defects in the SRAM core-cell. The position of the resistive-bridges has been chosen taking in account an actual industrial core-cell layout. We have performed an extensive number of simulations, varying the resistance value of the defects, supply voltage, frequency and temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array. Static and dynamic faults, single-cell and double-cells faults have been found.

In this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analyze industrial designs of SRAM core-cell at the following technology nodes: 90nm, 65nm and 40nm. We have performed an extensive number of simulations, varying the resistive value of defects, the power supply voltage, the memory size and the temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.

Negative Bias Temperature Instability (NBTI) is a degradation phenomenon that occurs in PMOS transistors during circuit lifetime. Recent works have proposed transistor level and circuit level models that allow designers to deal with such phenomenon. Based on these models and taking into account Random Dopant Fluctuation (RDF), we study the possibility of detecting SRAM core-cells that are prone to NBTI failures during post-production test. For this purpose, we introduce a statistical simulation method that allows estimating the amount of NBTI affected core-cells that pass or fail under given test conditions. Supply voltage, temperature, word line pulse width, word line pulse voltage and bit line voltage are the parameters considered as test conditions. An industrial core-cell design with a 65 nm technology is used as case study.