Network-on-Chip (NoC) architectures are widely used in many-core systems due to their scalability. Threedimensional NoCs further improve performance by stacking multiple layers using Through-Silicon Vias (TSVs), at the cost of increased routing complexity. Deterministic routing algorithms often suffer from congestion under non-uniform traffic, motivating adaptive solutions. In this paper, we present a learningbased adaptive routing approach for 3D NoCs that stabilizes Q-learning-based routing decisions using a beta-regulated probabilistic selection mechanism. Direction-based learning is employed to reduce learning complexity. Experimental results show improvements in latency and throughput compared to deterministic and conventional adaptive routing schemes.
This work investigates proposed maximum-powerpoint tracking (MPPT) approaches for a fully integrated hybrid voltage converter (H-VC) intended for alternative energy sources in low-power Internet of Things (IoT) systems, where passive components and power supply rail stability impose severe constraints. A monolithic Hybrid-Dual-Path (HDPC) voltage converter with an on-chip $L_{\text{DC}}=15.07 n H$ inductor and strongly limited total capacitance ($C_{\text{IN}}=C_{\text{OUT}} \approx 2.5 n F$) is considered, with 1.5 V output voltage regulation provided by a continuously operating shunt-type regulator. The two MPPT concepts are analyzed: (i) iMPPT based on the fractional open-circuit-voltage (FOCV) principle, which is energy-efficient but requires periodic $V_{\text{IN,OC}}$ sampling via short-time disconnection of alternative energy sources (AES), and (ii) oMPPT, which maximizes extracted load power by optimizing the combined product $\eta_{\text{MPPT}}.\eta_{\text{VC}}$ and provides instantaneous power observability in a form of digital code. The feasibility and performance are evaluated in Cadence using a TSMC 65 nm CMOS technology and a realistic PV model (KXOB25-14X1F), across irradiance levels of 5-500 W/m2 corresponding to PIN,MPP from $114 \mu W$ to 14.8 mW. Simulation results show that both approaches regulate operation over a wide switching-frequency span of roughly 0.9-62 MHz via FrequencyShift Modulation Control (FSM-C). Overall, iMPPT is favored when minimal control overhead is paramount, whereas oMPPT offers superior scalability and algorithmic flexibility for broader AES applicability at the cost of up to 5.5 times higher power consumption.
Post-Quantum Cryptography (PQC) schemes, such as Learning with Errors (LWE), rely on adding Gaussian noise to arithmetic operations to achieve security against quantum adversaries. Efficient generation of this noise is critical for hardware implementations, particularly in resource-constrained environments like IoT devices. Traditional approaches employ Gaussian samplers to produce discrete Gaussian noise, but these methods introduce significant area overhead and latency, limiting their practical applicability. In this work, we propose a novel hardware architecture that generates Gaussian-like noise using controlled XOR-based bit-flip operations integrated directly into arithmetic circuits. Our approach achieves up to a $3 \times$ reduction in area compared to conventional hardware Gaussian samplers, while introducing negligible delay. The resulting architectures provide an efficient and lightweight solution for noise injection, making them highly suitable for deployment in constrained hardware platforms.
This work presents a low-power analog artificial neural network for Star Evolutionary Phase Classification, implemented in a mixed-mode integrated architecture. The design employs a Swish activation function in the input layer and a voltage-to-current Bump-AntiBump circuit in the hidden layer for energy-efficient computation. A current-mode feature correlator based on an Euclidean Distance Circuit performs similarity assessment between feature vectors, while a Loser-Takes-All circuit ensures reliable classification. All analog blocks operate in the sub-threshold region, enabling sub-microwatt power consumption with a 0.6 V supply. Implemented in TSMC 65 nm CMOS within the Cadence IC Suite, the proposed ANN achieves a median classification accuracy of 94.0 % and an average power consumption of 967 nW. Comprehensive corner and Monte Carlo simulations confirm robustness against mismatch and process variations. Compared to software implementations and prior analog classifiers, the proposed design demonstrates superior energy efficiency and high accuracy, making it well suited for wake-up analog front-end applications.
Deep neural networks (DNNs) have high computational and memory demands because they rely on multiplyaccumulate (MAC) operations and the amount of data that needs to be moved from the main memory to the compute unit. Since 2016, Systolic Arrays have emerged as a popular architecture for accelerating DNNs inference, although their performance is affected by multiple parameters, including the amount of used Processing Elements (PEs) and the dataflow. In this study, we perform a systematic evaluation of Systolic Array-based DNN accelerators using the ScaleSIM simulation framework to analyze different array sizes and dataflow configurations across different DNN models, measuring the effects of memory transfers, and execution latency across all DNN workloads, founding that dataflow option for routing data through an array is dependent on the specific workload; thereby, using moderate array sizes can achieve better performance than larger arrays, offering useful insights for Systolic Array-based DNN accelerators design.
Although wake-up power-supply noise (PSN) leaves a more profound mark on IC performance than run-time PSN, it has received little attention in contemporary studies. This article addresses this gap by presenting a comprehensive mathematical model of wake-up PSN and introducing a novel strategy to temporally spread its impact via frequency modulation during the IC's sleep-to-active transition. Bringing this concept to reality, a framework of Sweeping Variable-Frequency Clock (SVFC) synthesis was realized in SCL 180 nm CMOS. Rigorous postlayout simulations on Cadence Virtuoso at a supply of 1.8 Volt reveal its finesse-achieving sub-10ps jitter and nearly 50% consistent pulse width across all frequencies and all process corners. Finally, benchmark analyses under DIP-40 package model substantiate the effectiveness of the approach with an average 63.6% improvement in wake-up PSN and 65.7% current and power savings across circuits under test, demonstrating a pathway to mitigate wake-up PSN and enhance IC reliability.
The paper investigates the application of Artificial Intelligence (AI) algorithms in two critical areas of simulationbased verification: (1) the development of verification testbenches (2) debugging activities within simulation environments. The primary objective is to assess how AI can enhance the productivity of verification engineers and improve the overall efficiency and quality of verification workflows in industrial practice. The paper presents the role of functional verification in the chip development flow, reviews widely adopted verification methodologies, AI techniques already used for automation and analysis, as well as the recent state-of-the-art research activities targeting emerging verification challenges. A key contribution is the identification of a significant gap in publicly available, high-quality open-source datasets tailored specifically for training AI models in hardware verification tasks. To ground the discussion in industrial reality, the paper also presents results from a survey conducted among 50 verification engineers, providing insight into which parts of a testbench could most benefit from AI-driven code generation or AI assistance. By combining a comprehensive state-of-the-art review with empirical insights from industry practitioners, this paper provides a structured analysis of current limitations and outlines concrete future research directions aligned with realworld verification needs.
While optimizing for core hardware performancerelated target metrics, frameworks for approximate accelerators often overlook the reliability aspect. Approximated implementations obtained by these frameworks can potentially differ in terms of reliability and may impact the reliability of the overall system. In particular, approximation changes the data profiles transmitted between system modules, which can trigger crosstalk on interconnect lines and aggravate electromigration. We propose a two-stage process that performs a reliability assessment of the circuit interconnects after the approximate accelerator synthesis. Our approach aims to find the most reliable solutions from the approximate candidate circuits generated by an automated approximation flow. We then leverage Pareto-filtering to strike a balance between area, reliability, and accuracy. Notably, the selected designs achieve up to a 178% improvement in mission time compared to the original accelerator, and a 68% improvement over designs optimized solely for area. In addition, our methodology allows custom priority settings to be adaptable to a user's preference, thereby leading to circuits that meet diverse design constraints. Our experimental results show the effectiveness of our methodology in achieving superior trade-offs between area, reliability, and accuracy, hence uncovering a new dimension for approximate accelerator design methodologies.
As semiconductor technologies scale into advanced sub-micron and FinFET nodes, layout complexity continues to grow. Modern analog and mixed-signal (AMS) designs use many metal layers, dense routing, and tight device-level constraints to meet demanding requirements. In these layouts, structures like floating shapes create serious risks. They can introduce parasitic coupling, affect simulation accuracy, and increase Electrostatic Discharge (ESD) sensitivity etc. Floating-shape problems are well known in semiconductor layout. There is no widely adopted automated method for detecting these problems. Existing research focuses primarily on modelling and analysis rather than automated detection. This work presents a floating-shape detection software implemented in Cadence Pegasus using Pegasus Verification Language (PVL). The design method repurposes the ANTENNA rule to trace connectivity through stacked metals, device terminals and labels. Consequently, it provides a unique framework to address the problem of floating shapes.
Modern Intrusion Detection Systems (IDS) struggle to scale to $100+$ Gbps throughput, as typically, the MultiPattern Matching (MPM) stage overwhelms CPU resources. While FPGA-based acceleration offers a theoretical solution, its adoption in production environments remains negligible despite decades of research. This disconnect stems not from a lack of raw hardware performance, but from unmatched IDS requirements and seemingly invasive integration. In this paper, we propose a standardized, stateless offload architecture based on the DPDK rte_flow API that decouples hardware acceleration from complex IDS logic. By using the FPGA as a smart tagger that annotates packets with matched pattern IDs via a compact metadata interface, we enable inline, scalable, integration with existing IDS pipelines like Suricata. We validate this approach through a trace-driven co-design study, demonstrating that a small metadata budget of three pattern IDs per packet is sufficient to offload the vast majority of traffic, resulting in up to 57 % throughput increase. Finally, we survey state-of-the-art 100+ Gbps FPGA engines against our derived integration criteria to highlight the critical features that future designs must implement to enable practical deployment.
Resistive RAM (RRAM) has emerged as a promising technology for in-memory computing, allowing both storage and computation within the same physical substrate. Although its ability to perform analog computations, especially multiplyaccumulate (MAC) operations, has been effectively utilized in neuromorphic systems, there has been limited research on its applicability to Boolean logic synthesis. Existing approaches typically rely on graph-based representations of Boolean functions that are mapped to column-wise MAC operations on standard RRAM crossbars. However, these representations largely inherit binary fan-in constraints from conventional logic synthesis flows, resulting in limited exploitation of MAC-level parallelism and underutilization of available crossbar resources. In this work, we address this limitation by introducing the concept of multi-input OR-Inverter Graphs (m-OIGs), which allow OR nodes with fanin greater than two to better match the accumulation semantics of MAC operations. Experimental results on standard benchmark suites demonstrate that increasing OR fan-in consistently reduces both crossbar area and total evaluation cycles, leading to improved performance and more efficient use of RRAM crossbar resources, highlighting the importance of fan-in-aware logic representations.
This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from $\mathbf{1} \boldsymbol{\mu} \mathbf{A}$ to $\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at $\boldsymbol{I}_{\text {out }}$ of $100 \mu ~\mathrm{A}$ and $300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.
Efficient data clustering on edge devices with limited resources requires balancing algorithm complexity with hardware constraints. While the $K$-Means algorithm is straightforward to implement on hardware, centroid-based updates often perform poorly on non-convex clusters. On the other hand, spectral clustering can handle non-linear structures but is computationally expensive. This paper introduces a parallel accelerator in field programmable gate arrays (FPGAs) for real-time clustering based on the Potts model. We present a deterministic solver that uses a $\mathbf{3 2}$-core single-instruction multiple-data (SIMD) architecture with interleaved memory banks to allow conflict-free parallel updates. By mapping the Hamiltonian to an integer-only formulation suitable for hardware implementation, it reduces the requirements for digital signal processor (DSP) modules and improves logic efficiency and parallelism. Implemented on a Xilinx Kintex UltraScale+ FPGA, the solver converges in 3.07 ms for 4096 nodes, reaching a throughput of 1.33 million samples per second. Experimental results show the architecture achieves perfect clustering accuracy on the evaluated synthetic benchmarks and outperforms $K$-Means clustering in topological robustness, providing a scalable, high-accuracy solution for edge data analysis.
The growing demand for high-performance analog circuits requires innovative design methodologies that accelerate the design process while maintaining accuracy and reliability. Machine Learning (ML) techniques have recently emerged in Inte grated Circuit (IC) design, leveraging their powerful modeling capabilities across different design stages. This paper introduces a simulation-free design automation methodology using Artificial Neural Networks (ANNs) to enhance Flash-ADC design work flows. The proposed approach adopts a top-bottom hierarchical design strategy: ANNs replace simulators and designers, elim inating the need for time-consuming simulations or excessive design iterations. To demonstrate the method, an 8-bit Flash-ADC was synthesized. The results show that the proposed framework significantly reduces computational overhead and accelerates the design process, achieving ultra-fast within less than one second. The study presents a generalized approach for ADC design and a hybrid testbench setup for analog optimization, offering a scalable solution for other complex systems.
The semiconductor industry is adopting chiplets as an alternative to integrated circuit design. With adoption of off-the-shelf chiplets, supply chain attacks are likely to increase, making chiplet authentication essential. This work identifies post-stacking testing as the best phase for authentication and proposes a framework using existing industry standards. The framework includes a flexible authentication IP integrated into the chiplet design, compatible with various authentication methods; an IP insertion flow compatible with commercial DFT insertion tools; a secure module for the test environment; and the corresponding test procedure. Results show that chiplet authentication can be implemented without disrupting industry practices, with multiple authentication methods available based on the context.
Monte Carlo circuit simulation is impossible without statistical compact models capable of faithfully reproducing the probability distributions of the circuit components' electrical characteristics. While such models do exist for devices fabricated using established processes and working under typical operating conditions, this is not always true of emerging devices or ones working at cryogenic temperatures. Although approximation MOSFET models can be used in place of physics-based ones, making them suitable for statistical simulation usually requires detailed information about the distributions of the transistors' physical parameters, which are difficult to extract. We propose an alternative approach that relies solely on $I-V$ measurements of a set of transistors of various geometries. Based on these data, a conditional variational autoencoder (CVAE) is trained. It is subsequently used to generate arbitrarily large $I-V$ datasets that match the statistical properties of the training data. The model can smoothly generalize between the training cases, which also enables reliable generation of $I-V$ data for other transistor geometries than those used for training. This approach has been shown to reliably reproduce the probability distributions of various figures of merit of an operational amplifier.
The globalization of the integrated circuit (IC) supply chain has increased the risk of IC piracy. Analog and mixed-signal (AMS) ICs are particularly vulnerable, as their design demands specialized expertise and multiple tapeouts to meet specifications, while they have limited automation support and inflexible portability across technology nodes, making them valuable intellectual assets and attractive targets for piracy. IC locking has emerged as an effective countermeasure, with several AMS IC locking paradigms proposed to date. The core idea is to embed a key mechanism within the AMS IC to control its functionality, treating the key as the designer's secret. Correct operation is achieved only when the valid key is applied, while any incorrect key renders the circuit non-functional. Existing locking solutions for purely analog blocks face the challenge of ensuring this dual objective. In this work, we propose an optimizationbased methodology that jointly synthesizes the target circuit and its key mechanism, ensuring the objective is deterministically achieved. The methodology is validated on two widely used AMS circuits: a bandgap reference and an operational amplifier.
The Capability Hardware Enhanced RISC Instructions (CHERI) architecture provides fine-grained memory protection for systems, but introduces additional hardware overheads that may negatively impact performance. Evaluating and optimizing such secure architectures require benchmarks that explicitly exercise their security mechanisms. Despite the abundance of benchmarks for unhardened systems, security-aware benchmarks for CHERI-based architectures remain scarce. We address this gap by proposing a framework for generating security-aware benchmarks for CHERI-based RISC-V systems, leveraging the TestRIG tool and applying CHERI-specific post-processing to ensure valid capability usage. As a demonstration use case, we apply the generated benchmarks to evaluate an In-Memory Computing (IMC)-based acceleration of the CHERI tagged memory. Our results show best-case speedups between 6% and 11%, while also identifying scenarios in which the acceleration proves no performance benefit.
The increasing deployment of AI (artificial intelligence) on edge devices presents major challenges due to strict constraints on computation, memory, energy, and latency. Effective Edge AI systems thus require multi-objective optimization that balances accuracy, hardware efficiency, and reliability. The Horizon Twinning project AIDA4Edge tackles these challenges by developing methods for efficient and reliable AI on resource-constrained platforms. This paper presents key approaches explored within the project, including neural network quantization, hardware-aware neural architecture search, dynamic neural networks, and self-adaptive resilient AI architectures. Finally, these strategies are placed within a broader, biologically inspired paradigm, highlighting neuromorphic computing as a natural continuation of Edge AI efforts toward highly efficient and resilient intelligent systems.
The reliability of microelectromechanical systems (MEMS) becomes increasingly important due to the fast market growth, especially in medical, automotive, and aerospace applications, where high reliability performance under harsh environmental conditions is crucial. The aim of this work is to test the behavior and performance of two-dimensional (2D) resonant MEMS mirrors, which are driven electrostatically, under different temperatures. Therefore, six mirrors and their driver application specific integrated circuits (ASIC) are tested inside a temperature chamber, where the temperature is swept between -40°C and 90°C multiple times and different mirror parameters are logged for both axes of the mirrors and the results are evaluated afterwards. Especially the driving frequencies of the axes are monitored. The results show that there is a nearly linear inverse relation between driving frequency of the mirror's fast axis and temperature, as the frequency rises with a decreasing temperature, while for the slow axis the relation between frequency and temperature is more complex. Moreover, the operation of the mirror is stable over the tested temperature range, as no failures are observed.
