Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model (LLM) aided assertion generation approaches have recently achieved remarkable progress, existing methods are still unable to effectively identify the relationship between design specifications and RTL designs, which leads to the insufficiency of the generated assertions. To address this issue, we propose AssertGen, an assertion generation framework that automatically generates SystemVerilog assertions (SVA). AssertGen first extracts verification objectives from specifications using a chain-of-thought (CoT) reasoning strategy, then bridges corresponding signals between these objectives and the RTL code to construct a cross-layer signal chain, and finally generates SVAs based on the LLM. Experimental results demonstrate that AssertGen outperforms the existing state-of-the-art methods across several key metrics, such as pass rate of formal property verification (FPV), cone of influence (COI), proof core and mutation testing coverage.
Quantum Key Distribution (QKD) represents a pivotal protocol for enabling secure communication within a future quantum network. While existing QKD schemes, such as Differential Phase Shift (DPS) and Coherent One-Way (COW) protocols, have advanced secure communication, they also exhibit certain vulnerabilities that can compromise security under practical deployment conditions. Quantum memory is essential for enhancing quantum key distribution (QKD) systems, particularly those using entangled photon sources (EPS QKD) for secure key generation. By enabling the storage and retrieval of quantum states, quantum memory improves security and extends the range of communication, addressing challenges like channel losses. Integrating quantum memory allows for temporal separation between the entanglement source and measurement, facilitating the use of quantum repeaters and improving synchronization. Recent advancements in quantum memory technologies, such as atomic ensembles, have led to better storage times and retrieval efficiencies, making EPS QKD more robust and scalable. In this perspective we recently have developed the first Made in India room temperature warm Rubidium Ensemble based Quantum Memory unit, utilizing the coherent optical non-linear phenomenon of EIT, featuring an electronics-photonics control box and the Optics memory box. Outlining the synergy between Quantum Memory and EPS QKD, emphasizing their potential to transform secure communication we further made a tabletop Entanglement-based QKD (EPS-QKD) demonstration setup, leveraging polarization-entangled photon pairs as the foundation of the secure key exchange.
The ability of resistive memory (ReRAM) to naturally conduct vector-matrix multiplication (VMM), the primary operation carried out in neural networks, has caught the interest of researchers. The memristor crossbar is a suitable architecture to perform VMM and additionally offers benefits like in-memory computation (IMC), low power, and high density. Memristor-based neural networks are typically trained using a mechanism where weight computations are carried out on a host machine and downloaded into the crossbar. However, due to faulty memristors in the crossbar, a cell may not be able to store the exact weight values, which may lead to inference errors. In this paper, we propose a weight-sharing method to improve the self-fault-tolerance capability of memristor crossbar. In order to reduce the impact of faulty memristors, the weights are shared among different layers of memristors in a 3D crossbar. Simulation analyses show considerable improvements in the fault-tolerance capability of the crossbar.
TensorFloat32 (TF32) floating-point adders process machine learning and deep learning applications in mission-critical systems. The mission-critical systems operated in radiation or high-temperature working conditions. These environmental conditions may be susceptible to single-event upsets (SEUs). The SEUs will result in incorrect outcomes, which may cause system failure. SEUs can be abolished by incorporating fault-tolerant techniques into the adder circuits. However, the primary concern is the hardware overhead associated with these circuits, which leads to more delay. So, to address these challenges, propose a Preferential Fault-Tolerant (PrFT) TF32 floating-point adder. The proposed adder architecture was developed using an error-analysis approach, which involves a preferential method to select the most critical hardware for applying TMR to mitigate faults as well as to reduce hardware cost and delay. The hardware reduces the 39.97% compared to the Triple Modular Redundancy-based TF32 adder. To evaluate the performance and efficiency of the proposed work, we conducted simulations and implemented the design on a Field-Programmable Gate Array (FPGA).
Logic obfuscation is a crucial technique in hardware security aimed at shielding integrated circuits (ICs) from threats such as reverse engineering and intellectual property theft. This research introduces an innovative approach by incorporating transmission gates into logic obfuscation mechanisms to bolster security within SRAM arrays. We propose and implement a distinctive locking mechanism utilizing transmission gates, applied to the word lines of a 4x4 SRAM array. This mechanism effectively regulates access to the memory cells, ensuring that data can only be read or written with the correct key input. To assess the efficacy of our approach, we evaluate the transistor count, power consumption, write access time, and read access time of the obfuscated SRAM array in comparison to a conventional, non-obfuscated SRAM array. Our experimental results reveal that, although the locking mechanism leads to a slight increase in power consumption, write access time, and read access time, these changes are minimal and within the range of typical circuit variations. The proposed method significantly enhances SRAM array security with only a marginal impact on performance, demonstrating its potential for safeguarding sensitive data in digital systems
The growing demand for advanced infotainment systems, convenience features, and safety measures in automobiles has led to an increase in the semiconductor content in automobiles. At the heart of these electronic systems lies the microcontroller, which requires thorough verification to guarantee proper functioning over the lifetime. Post-silicon characterization plays a vital role in guaranteeing that the microcontroller meets the specifications outlined in its datasheet. There are several challenges in completing the characterization of an automotive product on time. This paper summarizes the top four challenges encountered specifically in the hardware used for microcontroller characterization and the innovative solutions for these challenges. The main challenges are reliability of the hardware and the cost. The reliability of the characterization hardware is affected by connector quality, frost formation during cold temperature test and bow & sag of the boards. Ensuring reliability is important to avoid re-work which will delay the customer samples eventually impacting the product’s commercial success. The hardware cost is critical because it accounts for roughly 30% of the total characterization work package cost. The solutions explored are usage of spring pin interposers, integration of purge systems to stiffener and a reusable board concept. It is shown that the solutions help reduce 90% of the hardware cost and reduce the instances of board down-time by more than five times.
The demand for executing neural network (NN) learning and inference on edge devices is increasing. Memristor crossbar (MC) devices in neuromorphic computing (NC) provide a promising solution for accelerating NNs. However, immature fabrication technology makes faulty memristors inevitable, and the presence of stuck-at faults (SAFs) in MC devices substantially reduces the inference accuracy of NC System. The existing fault-resilient methods, which depend on mapping and retraining algorithms, cause costly and time-consuming processes with hardware overhead. This paper proposes a reliability-aware design framework for an NC system utilizing MC devices by combining fault-resilient training and IC-specific mapping. First, we apply fault-resilient training to enhance the robustness of the NN model. SAF-injected training is developed in this phase to mitigate the effects of SAFs. Then we map the weights of the trained model to MCs. The proposed framework preserves the inference accuracy without re-training, even though MCs are suffered from SAFs. Our proposed method is assessed using two different NN applications across two distinct datasets. The experimental results show that the proposed framework achieves high inference accuracy for several differently faulty MCs and enhances the reliability of NC system.
The increasing complexity of automotive SoC systems, particularly in the context of autonomous vehicles, demands rigorous functional safety verification methods. This paper proposes a novel Functional Safety FPGA Fault Injection Tool (FSF-FIT) which builds an FPGA-based emulation platform by using FPGA fault injection techniques. The core innovation of FSFFIT lies in its comprehensive FPGA functional safety evaluation process, targeting specific components within the Design Under Test (DUT), down to individual LUTs or registers. This detailed approach allows for accurate reliability level (RL) and diagnostic coverage (DC) assessments of safety mechanisms. The speed and accuracy of FSFFIT were validated through experiments conducted on the XuanTie C906 RISC-V processor as well as on a multiplier with different security mechanisms. The results demonstrated that FSFFIT’s performance is consistent with that of SSIM, a certified ISO26262-compliant functional safety tool, while also achieving faster execution times. Additionally, by comparing the results with some state-of-the-art (SOTA) FPGA fault injection tools, our method is superior in terms of injection speed.
Utilizing large language models (LLMs) for code generation has greatly enhanced software development. However, despite the advances in automated code generation frameworks that incorporate self-repair strategies, successful outcomes are not always guaranteed. This led us to explore a different approach to improving code quality. So we implemented a brainstorm-select-repair framework. For a natural language query, our framework first generates multiple foundational code snippets. Then these snippets are tested on test cases, and a text-similarity-based algorithm is used to identify the most accurate code. If none of the generated code snippets successfully fulfills the test cases, our proposed self-repair strategy is used to rectify any flawed code snippets until a code snippet that can pass the test case is identified and then provided to the user. Based on ChatGPT3, our framework reached 89% Pass@1 on HumanEval dataset (at least 3% higher than ChatGPT-4 the best model to date on this dataset). Our framework also surpasses state-of-the-art methods and delivers superior performance on the HumanEval-ET, MBPP, and MBPP-ET datasets. To further validate our design rationale, we conducted comprehensive experiments and analyzed the impact of each component.
The IEEE IJTAG (Internal JTAG) or IEEE 1687 standard was introduced to streamline access to the on-chip sensors and instruments. The IEEE 1687 standard has been successfully deployed in several modern SoC designs, and the same IJTAG network is extensively used to deploy the streaming scan networks and other advanced test methodologies. The IJTAG network gives access to most of the security critical components, and its security is very important. Several researchers across academia and industry have proposed security solutions for IJTAG, which do not address all threat models holistically. In this work, we propose a comprehensive security technique to safeguard the IJTAG from both internal and external threat models. The proposed technique employs an encryption-based solution to protect the architecture against malicious external attackers and untrustworthy third-party test centers and IP core vendors. We compare the proposed solution with existing solutions as well as present the test time overhead and attack analysis.
Post-silicon verification is used to locate and eliminate the bugs that escaped from the pre-silicon verification. The most serious challenge for post-silicon verification is the limited observability of internal signals. Automatic signal selection technique is used to select a signal combination that can maximize the restoration of the untraced states to solve this challenge. In previous studies, structure-based technology and simulation-based technology cannot run fast and have a high restoration quality at the same time. Machine learning based technology have to select circuits as training set carefully. In this paper, i) we extend the restoration ratio to be applicable to FPGA netlist resources and ii) we propose a new signal selection technology using genetic algorithm which extends simulation-based technology and can achieve faster operation speed while ensuring the restoration quality.
Scan based diagnosis is an industry proven approach to aid in identifying the root-cause of defects in silicon. ATPG fault models such as stuck-at, transition are typically used for identifying the best possible fault location(s) that explain the potential reason for tester failures. With lower technology nodes, the correlation between behavior of defects in silicon and the modeled faults is quickly declining. Opens and Shorts either internal to library cells or the cell interconnects, timing defects at a specific location or on a specific path are some examples. With the addition of these new defect types, newer and complex fault models have to be considered for diagnosis. Each of these fault models will add substantial run time overhead to diagnosis making the yield analysis process longer. This paper proposes a new approach to perform diagnosis with all the newer fault models in a tractable time. Proposed approach allows simpler addition of newer fault models with marginal run time overhead. Experimental results indicate up to 2.97X run time reduction with proposed approach.
A Clock Mesh is a structure commonly used in System-on-a-Chip (SoC) designs running at very high clock rates, typically beyond 2.0 GHz, to distribute a clock signal across a large region of a chip. The clock mesh typically is implemented using wires on two adjacent and orthogonal levels of metal in a chip, in which the wires are tied together at each point of intersection. Taps of the mesh are made as needed to service the clocking needs of logic below the mesh. A typical tap would normally service the clocking needs of an area that is in the order of 0.01 sq mm. Several taps are placed beneath the mesh to ensure coverage of the entire area of the block. In some SOC Designs, two or more synchronous clocks are needed to support logic which is placed below the clock mesh. Typically, the synchronous clocks are divided clocks. To meet the timing closure requirements of the logic, when logic of one synchronous clock drives logic associated with the other synchronous clock, it is necessary to provide precise alignment of the clocks, including precise alignment of coincident edges of the synchronous clocks. In this paper, we propose a method of supporting the requirement of multiple synchronous clocks with a single mesh and meeting the Design for Test needs of such designs.
This paper targets reduction of RF testing costs, focusing in particular on the generation of modulated stimuli for testing the reception chain of RF communication devices. It proposes an innovative low-cost solution that can be implemented on a standard digital Automated Test Equipment (ATE). The approach relies on the generation of a baseband digital signal with specific encoding, and the exploitation of one of its harmonic replicas as RF test stimulus. Spectral integrity of the signal around the targeted harmonic replica is ensured through a careful selection of the ATE sampling frequency. A generic methodology for practical implementation is presented and illustrated in this paper considering two popular digital modulation formats, namely Binary Phase-Shift Keying (BPSK) and Minimum-Shift Keying (MSK). Experimental validation is performed using a microcontroller unit (MCU) capable of operating at a sampling rate up to 500Mbps. Results show that despite the limited sampling capability of the equipment, test stimuli with the desired spectral characteristics in the 433MHz and 868MHz ISM bands can be generated, validating the proposed solution.
Systolic arrays are a popular choice for accelerating deep neural networks (DNNs) due to their inherent parallelism and efficient data reuse. However, ensuring the reliability of these DNN accelerators is crucial, as hardware faults can significantly degrade inferencing accuracy. Because systolic arrays utilize a large number of processing elements (PEs) for parallel processing of matrix multiplication, dataflow involving faulty PEs is especially of concern. Error propagation through PEs can reduce inferencing accuracy for DNN workloads. Even though many algorithm-based fault tolerance (ABFT) algorithms have been proposed to detect and correct errors in matrix multiplication, these ABFT methods cannot detect many errors originating from the accelerator hardware. We propose a run-time based fault detection technique leveraging functional data to generate checksums on-the-fly, avoiding the requirement for test patterns. Experimental evaluation shows that the proposed fault detection architecture can achieve 100% test coverage while incurring an area overhead of less than 2% for a 256 x 256 systolic array.
With the emergence of all-inclusive AI/ML applications, hardware solutions, commonly known as AI-Accelerators (AIA), are now being widely adopted to emulate deep neural networks (DNN) to facilitate faster and large-scale data analytics. An AIA-chip comprises a 2D systolic array of identical processing units (PEs), registers, and glue logic. These arrays may be implemented with traditional digital logic or with analog primitives such as memristors. As the packing density of AIA-chips increases, they become vulnerable to various manufacturing defects thereby compromising yield and the accuracy of prediction. In this review article, we summarize various methods that have been recently proposed for expediting Automatic Test-Pattern Generation (ATPG) for stuck-at and transition faults in AIA-arrays. Other relevant issues such as fault-criticality, self-test, fault-recovery, and the asymmetry of fault behavior, are also discussed.
This paper proposes a formal approach and testing process for the failure modes of intelligent algorithms. The process first requires the establishment of a failure mode library specific to the algorithm domain. Subsequently, we introduce a formalized method for providing a standardized and comprehensive description of the failure modes. We developed a supporting system to parse the formal description statements, enabling the automatic generation of failure test cases based on the failure modes. Finally, we validated the effectiveness and practicality of our proposed testing process based on failure modes in the field of object detection algorithms, demonstrating the testing process’s outstanding effectiveness.
Stochastic computing (SC) provides low-area, power-efficient hardware solutions suitable for edge systems, but its scalability poses challenges due to its precision limitations, especially in noisy environments. This paper investigates the fault tolerance of key SC components, such as stochastic number generators (SNGs) and activation functions (AFs), within recurrent and sequential networks like long short-term memory (LSTM) networks. We inject bit-flip faults into a network’s most sensitive inputs, weights and AFs, and study fault propagation across different network layers. Our findings reveal that SC component choices significantly influence fault tolerance. For example, networks using Sobol-based SNGs with tanh AFs exhibited stronger resilience than those with LFSR-based SNGs and ReLU AFs, by maintaining higher accuracy under fault conditions. However, the accuracy of the networks declined significantly under simultaneous faults in inputs, weights and AFs. Additionally, while increasing stochastic number lengths improved fault tolerance, they also increased latency. Nevertheless, the SC networks achieved up to 54% area and 72% power savings, making them ideal for resource-constrained applications. We also found that there is a trade-off between efficiency and fault tolerance: SC designs that focus on resource efficiency may struggle in noisy environments, where fault-tolerant SC designs are more effective. This implies that fault resilience in SC architectures depend heavily on design choices and cannot be assumed inherent across all configurations.
NAND flash memory, known for its high-density storage and non-volatility, is widely used in various applications where reliable data storage is critical. Ensuring the integrity of stored data requires effective fault detection methods and correction mechanisms, particularly for stuck-at faults, which are common in NAND memory architectures. This paper focuses on testing NAND flash memory array, employing the March algorithm due to its proven efficiency in detecting such faults. This work demonstrates detailed modeling of floating-gate cell (FG Cell), a 4x4 memory array, sense amplifier, and decoders using HSPICE. Simulation results illustrate electrical behavior of the modeled components.The results demonstrate that the March algorithm efficiently detects stuck-at faults within the memory array, enhancing the reliability and performance of NAND memory systems. The HSPICE modeling provides accurate insights into the behavior of memory cells, sense amplifiers, and decoders under various conditions, offering a robust framework for future memory testing and verification efforts.
Recent advancements in semiconductor technology nodes, makes it possible to accommodate large number of transistors in single System on Chip (SoC) to achieve intended functionality. It has always been challenging to test such highly area dense logic of SoCs at its functional/ operational speed with optimized test time and within its functional power consumption limits. ATPG is the most effective and efficient method of structurally testing the digital logic, which involves sequentially loading and un-loading of the scan chains. All design flip-flops in the SoC toggles in a random controlled fashion during ATPG test and lead to design toggle activity much beyond the functional threshold limits. The design power grid needs to be robust enough to cater to the demand current during test, otherwise this could lead to failures and yield loss in production test. Application of ATPG test is limited by average and peak power consumption of the device under test. This paper witnesses several proposed power aware test methodologies, which has contributed to minimize scan peak IR drop from more than 50% to within acceptable limit along with peak current reduced from 1A to 0.2A and contributed to nullify yield loss due to test power. Proposed power aware test methodologies are implemented in 45nm Industrial SoC designs and from volume data silicon results proves practical effectiveness of it.
