On-chip SRAM protection has become a fundamental requirement in modern secure Systems-on-Chip (SoCs), driven by increasingly stringent low-power reliability and security standards. To counter Volt Boot and Cold Boot attacks, recent defenses predominantly rely on True Random Number Generator (TRNG)-driven address and data (de)mapping schemes designed for resource-constrained environments. However, such uniform TRNG-based XOR mapping mechanisms, are intrinsically vulnerable to optimization-based cryptanalysis due to their inherent linearity. In this paper, we present a chosen-plaintext attack based on Particle Swarm Optimization (PSO) that exploits this linear structure to recover protected memory contents. Across nine experimental configurations with key sizes ranging from 128 to 512 bits, the attack achieves complete memory recovery with perfect reconstruction accuracy ($N M S E=\mathbf{0}$ and $S S I M=\mathbf{1. 0}$). Moreover, the effective search space is reduced by up to $\mathbf{1 0}^{147} \times$ compared to exhaustive brute-force exploration, underscoring the practical insecurity of linear XOR-based TRNG mapping schemes. To mitigate this vulnerability, a group-based SRAM address and data (de)mapping architecture is introduced that disrupts global linear dependencies while preserving standard access latency. The experimental results demonstrate a substantial degradation in the effectiveness of the attack, obtaining NMSE values in the range of 0.117 to 0.279 and $P S N R$ between 5.54 and 9.30 dB, corresponding to approximately 99.7% corruption of the reconstructed data. The proposed countermeasure achieves this enhanced security with negligible hardware cost, incurring less than 0.4% area overhead.
Hyperdimensional Computing (HDC) is a neuroinspired paradigm ideal for hardware acceleration that is resilient to noise and faults. Despite this potential, the literature on fault analysis in HDC has focused almost exclusively on associative memories, overlooking the functional units of the accelerator itself. To address this gap, this work investigates the vulnerability of a custom open-source HDC hardware accelerator through transient fault injection-not within the associative memory, but in the functional units responsible for hypervector processing. Our fault injection campaigns, using simulation and real proton injection, show that higher hypervector dimensionality improves fault tolerance in data, even within the accelerator. However, control and addressing signals are more susceptible, leading to permanent write errors.
Efficiently storing memory test outcomes by preserving exact failure information in Automotive Systems-on-Chip is currently one of the major test challenges. Due to the limited availability of the on-chip buffer memory and the non-negligible time needed to transmit test results, their exact failing coordinates may be wasted due to the buffer saturation. To overcome this limitation, an efficient approach is to compress the detected faults using on-chip test resources, enabling the tester to retrieve the fault information at the end of the memory test. Although this method achieves significant memory savings, it does so at the cost of losing the exact failing bitmap coordinates, thereby introducing a lossy compression effect. To solve this issue, this paper proposes a framework relying on super-resolution (SR) artificial intelligence models to reconstruct off-chip, with high accuracy, the failing bitmaps. On-chip 256x256 coordinate-based failing bit test results are saved in a compressed format using $16 \times 16$ bitmaps. This compressed diagnostic information is then fed off-chip to the SR framework to return very accurate fullchip predictions on $256 \times 256$ bitmaps. As a case of study, the developed SR model has been trained on a dataset composed of real industrial failing RRAM results, achieving 98% accuracy. Overall, the off-chip proposed methodology achieves high global SR scores: competitive metrics adopting Structural Similarity Index Measure (SSIM) have been used, and all return results above 98% accuracy of reconstruction.
Interest in Near-Memory Computing (NMC) architectures continues to grow due to their ability to reduce data movement between processing and memory units, improving latency and energy efficiency. Beyond this, the computation capabilities available in the NMC logic layer open a new and unexplored opportunity to exploit these resources for memory testing at lower cost. This work introduces a fully programmable Finite State Machine (FSM)-based MBIST solution dedicated to NMC architectures. By supporting multiple test algorithms, it enables flexible fault coverage for both production testing and in-field diagnostics. The key novelty lies in reusing existing NMC logic layer resources to reduce BIST hardware overhead while leveraging NMC parallelism to accelerate test execution. Simulation and synthesis results show that, for a $\mathbf{1 K B}$ case-study NMC architecture, the implementation requires only 5.7% hardware overhead and achieves a $9.5 \times$ speedup over a CPUbased approach while preserving full algorithmic flexibility.
RISC-V is increasingly considered a strategic architecture for technological sovereignty and long-term platform independence, yet its practical maturity across software, performance and security is still debated. This paper presents an integrated, hardware-grounded assessment of the current RISC-V ecosystem. We first analyze software readiness by examining toolchain fragmentation, operating-system integration, and deployment effort across commercial ASIC boards and configurable FPGA soft-cores. We then benchmark representative processors using CoreMark, Geekbench 6, and SPEC2017, and contextualize the achieved results through direct comparison with contemporary ARM and x86 systems. Finally, we evaluate susceptibility to Transient Execution Attacks on three prominent open-source cores (BOOM, NOEL-V, and CVA6). The results show a clear three-way trade-off. Software support remains heterogeneous: ASIC platforms provide faster bring-up, whereas soft-core deployments require substantial hardware-software codesign effort. From a performance perspective, the best evaluated RISC-V ASIC demonstrates competitive per-cycle efficiency for embedded-class workloads, but a significant gap persists versus high-end proprietary processors; on FPGA soft-cores, low frequency and memory-system constraints often prevent completion of demanding benchmark suites. From a security perspective, all evaluated open-source cores are vulnerable to a subset of transient-execution attacks, with broader attack surfaces associated with more aggressive speculative microarchitectures. Overall, RISC-V is already a deployable opportunity for customizable embedded domains. For high-performance, general-purpose use, closing the gap requires coordinated ecosystem consolidation and rigorous security-by-design co-validation across hardware and software layers.
This paper encompasses three contributions by university professors and researchers. The presentations vary from the state-of-the-art of VLSI benchmarks for testing and reliability and their importance for the research community, to the advent of new benchmarks to address the current complexity gap with industrial designs and enable researchers to effectively validate their methodologies.
Modern System-on-Chips (SoCs) increasingly integrate time-to-digital converter (TDC) based on-chip timing monitors to enable self-awareness for dependability-related applications. These monitors offer sub-clock cycle resolution but are highly sensitive to on-chip variations such as process, voltage, and temperature (PVT), transient voltage droop, and long-term selfaging effects. As a result, in-field calibration of these monitors becomes inevitable for achieving reliable measurements. This paper proposes a fast, single clock cycle calibration methodology that enables simultaneous calibration of multiple TDC-based timing monitors operating in the same voltage domain in an SoC. The novelty of this approach lies in the use of a shared, per-voltage-domain calibration IP instead of per-monitor selfcalibrating logic, which significantly reduces the area overhead associated with a monitoring infrastructure. Furthermore, the proposed IP is suitable for calibration against fast-changing phenomena like voltage droop as well as slower variations like PVT and aging. In addition to the conventional TDC-based positive slack monitor, design for a negative slack monitor is also discussed, which estimates negative slack during late signal transitions by sampling the transitioning signal immediately after the capturing clock edge. This enables in-field estimation of both positive and negative slack, supporting adaptive mechanisms for resilient system operation. Post layout evaluation of the proposed IP and the timing monitor is presented using the TSMC 65 nm standard cell library. Results demonstrate that the proposed calibration method reduces the average magnitude of error (RMSE) in slack measurement by 46%.
Post-quantum cryptography addresses the threat posed by large-scale quantum computers to current public-key cryptosystems. After an eight-year evaluation process, NIST has standardized ML-KEM, a quantum-resistant scheme for publickey encryption and key encapsulation, whose global deployment is anticipated by 2035. Beyond algorithmic security, the resistance of physical implementations of ML-KEM to sidechannel attacks is important for a secure transition. This paper evaluates the resistance of a software implementation of MLKEM protected against side-channel analysis using masking and shuffling. Despite these countermeasures, we can recover the secret key using only one third of the traces compared to the state-of-the-art attack. Our main contribution is a novel chosenciphertext construction method that 1) circumvents the shuffling countermeasure, and 2) overcomes the inter-device variation problem. This method is applicable not only to ML-KEM, but also to other lattice-based PKE or KEM algorithms. We provide an in-depth analysis of the attack methodology, validate the attack on an ARM Cortex-M4 platform recommended by NIST for benchmarking, and suggest potential countermeasures for hardening ML-KEM implementations against side-channel attacks.
The increasing complexity of semiconductor technologies is exposing limitations in traditional manufacturing test methodologies. Although fault-model-based testing has enabled efficient production screening for decades, growing evidence from advanced logic and memory technologies indicates that many realistic defect mechanisms are insufficiently represented by conventional fault abstractions, leading to test escapes and in-field failures. This paper examines three directions for improving outgoing product quality. First, we discuss the growing mismatch between fault models and actual silicon behavior and emphasize the need for silicon-informed assessment of defect coverage. Second, we investigate timing failures caused by process-variation-induced delay marginalities, which increasingly evade conventional scan-based delay testing. Finally, we present Device-Aware Test (DAT), a defect-centric methodology that derives fault models and test solutions directly from physical defect behavior. Examples from STT-MRAM, RRAM, and FeFET memories demonstrate how DAT enables the detection of realistic defect mechanisms beyond the reach of conventional approaches. Together, these directions support a transition toward defect-aware, data-driven testing for future semiconductor systems.
With the advent and quick improvement of quantum computers, conventional cryptographic systems will become vulnerable in the near future, creating a high risk in security and privacy. For this reason, post quantum cryptographic schemes have been developed which impose new hardware and software requirements to existing and upcoming hardware. While there are several works in the literature focused on post quantum cryptography acceleration in general purpose, high performance systems, the vast majority of computing devices, i.e. embedded, Internet of Things are not covered by them, due to their high area, power or memory cost. In this tutorial, we will focus on the particular case of these devices. The tutorial includes the active standardization activities in various bodies particularly focused on RISC-V, as well as on-going efforts in European Commission funded research projects, such as PQC4eMRTD and SMARTY.
The adoption of non-conventional architectures assuming not only CMOS, but also emerging devices - has been explored for guaranteeing the development of highperformance edge AI hardware. In more detail, the braininspired computing paradigm has been explored in order to overcome one of the key computing architecture walls, the vonNeumann bottleneck. In parallel, novel device technologies, such as Resistive Random-Access Memories (RRAMs) have been developed to address the limitations related to the CMOS technology scaling, more precisely the reliability and leakage power walls. In this context, the idea of developing braininspired architectures based on technology heterogeneity for developing high-performance edge AI hardware represents a very promising solution for overcoming the previously mentioned challenges. However, despite the clear advantages, the adoption of these non-conventional architectures assuming CMOS and RRAM-based circuits depends on being able to guarantee not only their quality at time zero, but also their reliability during lifetime. In this context, this paper introduces the key challenges related to brain-inspired architectures, assuming a heterogenous integration of CMOS and RRAM devices, describing the sources of quality and reliability issues assuming a holistic approach that includes all lifecycle phases related to hardware development. Finally, this paper provides a discussion related to the use of RRAM devices for implementing brain-inspired computing architectures and summarizes strategies able to guarantee highly reliable edge AI architectures.
As semiconductor process nodes scale below 5 nm, degradation mechanisms such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) necessitate increasingly pessimistic voltage guardbands. Current Adaptive Voltage Scaling (AVS) techniques rely on reactive hardware monitors, which effectively detect aging but require a fixed “safety margin” (typically $30-50 \mathrm{mV}$) to account for monitor inaccuracy and transient voltage droops. This paper introduces Actuarial Voltage Scaling (AVS+), a novel Cyber-Physical System (CPS) control loop that manages silicon aging as a stochastic plant. By adapting Survival Analysis principles from actuarial science-specifically the Gompertz-Makeham law of mortality-we model the “time-to-failure” of processor cores as a stochastic process. Unlike reactive AVS, the Actuarial controller predicts degradation drift and transient risks before they manifest, allowing the guardband to be dynamically minimized based on model confidence. We validate this framework using a calibrated simulation of a $\mathbf{1 0 2 4}$-PE Systolic Array under AI tensor workloads. Results demonstrate that AVS+ maintains ISO-reliability while reducing the average voltage guardband by 65% compared to standard AVS, translating to significant energy savings in power-constrained high-performance computing (HPC) environments.
The stress test of integrated circuits is becoming a significant factor in their production cycle in all application domains. This paper presents a methodology which can be used to quantify the actual stress coverage of Time-Dependent Dielectric Breakdown (TDDB) in arbitrary designs with standard logic cells in an Electronic Design Automation (EDA) flow. The methodology also provides an estimate of overstress or understress. The concept is based on the cell-aware transistor-state stress model (TSSM) that exploits the activity and switching of transistors in the standard cells with an N-detect approach. The experimental results are illustrated on productive designs in deep submicron technologies.
Through Silicon Via (TSV) plays an important role as the vertical interconnection component in the $2.5 \mathrm{D} / 3 \mathrm{D}$ integrated chips. In the post-bond testing phase, the TSV defects can be characterized by the transmission delay of TSV. Most of the post-bond TSV test methods deploy the signal generator and detector circuit in the adjacent dies, in which the crossdie synchronization limits the test accuracy. This work proposes a new test method for the post-bond TSVs. The test circuit is deployed for each $2 \times 2$ subarray. The TSVs in each subarray are connected in series by switches, and the TSV defects are tested by the time-digital converter based delay detector. Both the signal generator and the delay detector are set at the same die to simplify the synchronization mechanism. Different TSV subarrays can be tested in parallel. The Elmore delay model of transmission line is applied to the TSV signal path to enhance the delay resolution, and multi-configurations of the intra-subarray TSV signal paths are able to localize the faulty TSVs. Simulation results show that the proposed method achieves good test performance with relatively small area overhead.
Single Event Transients (SETs) pose a critical reliability challenge as technology scaling increases sensitivity to ionizing radiation. This paper presents a novel two-stage Machine Learning (ML) framework to predict SET waveforms across diverse gate types, PVT conditions, and process nodes. The methodology first predicts fundamental pulse characteristics, which then serve as features for a secondary model to reconstruct the full temporal waveform. Characterization is performed using bias-dependent SPICE simulations across five technology nodes $(130 \mathrm{~nm}$ to 2 nm). The models demonstrate robust cross-technology generalization. Specifically, the LightGBM-based architecture achieves a Mean Absolute Percentage Error (MAPE) as low as 3.75% on advanced nodes such as IMEC 2 nm. Furthermore, by incorporating a few-shot learning approach, the prediction error is reduced to approximately 2.6%, while only requiring 68.4 seconds on average. This framework enables rapid and scalable SET susceptibility analysis, making it suitable for integration into advanced reliability-aware design flows.
Recent studies indicate that resource-efficient online fault detection in dependable computing systems may rely on probabilistic data structures such as Bloom and Cuckoo filters. To be effective and lightweight, these filters require low-latency and resource-efficient hash-to-index mappings. Existing approaches, namely, modulo, power-of-two, and multiplicative indexing, either incur high implementation cost, latency overhead, or impose rigid table size constraints that can lead to over-provisioning and suboptimal memory utilization, limiting their adoption in embedded and real-time systems. To address these limitations, this work proposes a hardware-efficient hash-to-index reduction technique based on rejection sampling. The proposed method optimizes index computation, yielding a uniform distribution for arbitrary table lengths while avoiding costly division or multiplication. Implemented as a mask-then-reject datapath on FPGA, our approach enables lightweight online checkers that maintain low area and latency footprints without sacrificing correctness. Experimental results on Bloom and Cuckoo filters demonstrate similar detection accuracy compared to canonical mappings while reducing hardware cost and latency.
Modern systems-on-chip integrate numerous embedded test instruments accessible through an IEEE 1687 (IJTAG) network. These instruments often operate in asynchronous clock domains, requiring robust interfaces for reliable data exchange. While synchronizer-based interfaces are commonly used, they exhibit significant limitations at high IJTAG clock frequencies. Existing clock-gating and multiplexing solutions remain incompatible with clock mesh methodologies widely adopted in modern designs. This paper introduces a novel self-adapting asynchronous interface that automatically adjusts IJTAG instrument operations, such as memory BIST, to match IJTAG clock characteristics while maintaining full compatibility with clock mesh architectures. The technique also adapts to IJTAG control signal stretching and TCK duty cycle variations. Simulation results demonstrate reliable operation, enabling efficient instrument test access in advanced semiconductor processes.
The state of health (SoH) is a key indicator of Li-ion battery aging, usually reflected by capacity degradation over time after successive charging and discharging cycles. Even though centralized deep learning (DL) methods have achieved promising results, the data used for training and inference must be stored on a single server, raising concerns about data privacy, confidentiality, and scalability. Federated learning (FL) addresses these concerns by enabling distributed training among different clients using their own data and aggregating the weights on a centralized server. Therefore, in this paper we propose an edge-based FL system specifically designed and evaluated for reliable battery SoH prediction. The client-side is represented by a custom-built Raspberry Pi 5 cluster, while the server in our setup is represented by a laptop. Experiments were conducted using the NASA July 2025 battery dataset. Three DL architectures are integrated and compared at both the client and server levels of the FL environment, namely long-short-term memories (LSTM), gated recurrent units (GRU), and a hybrid attention-enhanced architecture composed of one-dimensional convolutional neural network (1D CNN) followed by two LSTM layers. Detailed performance evaluations, including predictive robustness, consistency, latency, and energy consumption measurements on the edge devices are presented. The results highlight the feasibility and reliability trade-offs of deploying federated SoH prediction systems at the edge.
Transformer-based models are being deployed in safety-critical domains such as autonomous systems and healthcare, where reliability is important. Fault tolerance is crucial when a model’s stability is impacted due to transient and permanent hardware faults. However, fault analysis and mitigation in these architectures remain limited. Thresholding, quantization, and a new method called Bit Mask can be used to mitigate the accuracy degradation caused by bit-flips in hidden states. To validate these methods, we simulated faults by injecting errors in the hidden states of the model. Both fine-grained and coarsegrained thresholding methods improved resilience with reduction in the metric drop from 41% to below 1% and the accuracy degradation for Bit Mask reduced to less than 2.5%. Our work also conducts an extensive fault injection campaign on Query, Key and Value weight matrices of transformer models revealing the Value weight matrix as most critical, particularly at the third exponent bit.
Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising nonvolatile memory technology; however, its low on/off resistance ratio renders read reliability highly susceptible to process, voltage, and temperature (PVT) variations. To improve read reliability, STT-MRAMs typically employ a trimmable reference resistance scheme alongside a trimming test to determine an appropriate reference resistance. This paper proposes a simulation approach to quantitatively analyze various reference trimming schemes. Two global trimming schemes are explored in relation to different array configurations, variation severities, and tunnel magnetoresistance (TMR) ratios. The results compare reference resistance accuracy and read margins, demonstrating the trade-offs and effectiveness of these schemes in enhancing read reliability.
