We present two wafer backside-frontside connection schemes for backside power delivery networks: (1) buried power rail combined with self-aligned nanoscale TSV, with ~250 nm of remaining Si substrate; (2) through dielectric via without remaining Si substrate. Integration flows of these two schemes are detailed. Different thinning approaches are compared. Intensive electrical and thermal characterizations have been done, including resistance, capacitance and heating rate (temperature increase as a function of applied power). It is exhibited that the remaining 250 nm Si substrate can reduce the heating rate of no remaining Si scheme from 100 K/mW to 50 K/mW. Meanwhile, a solid consistency between measurement and simulation has been achieved, in terms of both capacitance and heating rate characterizations.

We demonstrate for the first time a two metal level Ru interconnect using fully self-aligned vias (FSAV) landing on 16 nm metal pitch (MP). M-x lines are patterned using EUV-SADP and direct metal etch of Ru in a spacer is dielectric (SID) integration scheme. With a critical dimension (CD) of 8 nm Mx lines measure an average of 670 Omega/mu m with a yield of >95% across a 300 mm wafer and average resistivity of 15.5 mu Omega.cm extracted from TCR measurements. FSAV via performance is competitive with a measured resistance value of 14 Omega for >95% yield across the full wafer. This effort is a crucial step towards the tight pitch requirements of standard cell scaling and CFET implementation.

A resonant clock-power distribution network is critical for scaling energy efficient superconducting digital technology to practical high integration density circuits. High-k, tunable capacitors enable implementation of a resonant power delivery network supporting circuits with up to 400 Mdevices/cm2. We report the cryogenic characterization of Metal-Insulator-Metal capacitors using a Hafnium Zirconium Oxide (HZO) ferroelectric insulating layer and Niobium Titanium Nitride (NbTiN) superconducting electrodes. The fabricated chip includes capacitor arrays for low frequency characterization and a half-wave transmission line resonator for RF characterization. A specific capacitance of 3 uF/cm2, DC leakage current of 10-8 A/cm2 at 2 V and a constant 5 percent tunability up to 4 GHz were measured at 2.6 K.

This study investigates the overlay performance of a 2-level Ru semi-damascene integration using a Spacer-is-Dielectric (SID) SADP strategy to create 18 nm metal pitch Ru metal lines combined with fully self-aligned vias (FSAV). Furthermore, the impact of via overlay on FSAV electrical performance was experimentally assessed. Results show that <= 3 nm lot M(x)block-to-M-x overlay residuals can be achieved using an SID-SADP approach with TiN as hard mask. Moreover, an >80% kelvin via yield could be obtained for a via y-overlay range of 10 nm and via x-overlay range of 11 nm, highlighting the FSAV process's robustness for future interconnect scaling.

In this work, we present an optimized two-metal level (2ML) BEOL unit process based on NbTiN developed in imec's 300mm pilot line. Vias with varying critical dimension (CD), pre-clean conditions, and metal fill depositions were explored to mitigate the formation of voids in the vias upon PVD deposition into the cavities. A range of via CDs down to 40 nm were produced using lithography bias. NbTi alloy target deposition improved wafer resistivity relative standard deviation by 50% compared to co-sputtering, improving wafer uniformity. Different integration routes were evaluated to fabricate NbTiN wires while minimizing sidewall oxidation and electrical CD losses. Critical currents were up to 2x better than previously reported via-chain devices. Wire CD loss was reduced by at least 7 nm. Wire critical currents are similar for top and bottom layers, indicating no degradation with additional processing. The critical current density is up to 95 mA/mu m(2), which is greater than half of the theoretical depairing current density of our thin films.

This work presents the integration of MP16/18 in a spacer-is-dielectric SADP Ru semi-damascene integration scheme through a novel SiN-based core and gap hard mask integration flow. This approach lowers the cost of single metal layer processing by 60% compared to a metal-based core approach. It also enables more than 80% yield on MP18 lines and the first ever reported electrical measurements of MP16 line structures in literature achieving 40% yield across a 300mm wafer, with an average resistance of 524 Omega/mu m (MP18) and 656 Omega/mu m (MP16). MP18 leakage structures show a low line-to-line leakage at 1.2V achieving 80% yield with a breakdown voltage in the range of 8-11V.

This work reports variable metal width Ru semi-damascene bottom metal line integration at metal pitch (MP)=18-26 nm, for the first time at high-aspect ratios of 4 and 6. It is also the first report on routing of such lines to a top semi-damascene metal level using a fully self-aligned via (FSAV). Average core-gap line resistance (R) at MP=18 nm is similar to 240 Omega/mu m at AR6. Line-line leakage yields of 50% and 30% at AR4 and AR6, respectively, is achieved at MP=18 nm which exceed 90% and 70% at MP=20 nm. MP=18 nm, AR4 line-line TDDB at 100 degrees C show an extrapolated failure time of >10y. Ru FSAV fabricated on AR4, MP=18 nm Ru line has a kelvin resistance of similar to 20 Omega at via bottom CD similar to 9.4 nm and via height similar to 8.4 nm. Electromigration (EM) on single vias show robust Ru-Ru interface with no failures post 135h of EM stress at similar to 10 MA/cm(2) and 330 degrees C.

In this paper we present a superconducting two-metal level (2ML) BEOL unit process based on NbxTi(1-x)N (NbTiN) that was developed in imec's 300 mm pilot line using a semi-damascene flow and 193i lithography. The unit process features direct-metal-etch wires with minimum critical dimension (CD) of 50 nm and shallow planarized vias with minimum CD of 80 nm deposited at 420 degrees C, compatible with CMOS BEOL dielectrics. Normalized line resistance of 50 nm NbTiN wires show that 95% of the devices meet the expected resistance 800-1200 Omega/mu m consistent with blanket films resistivity. Low temperature measurements show that NbTiN wires and vias have a critical temperature of 12-13.5 K and a critical current density of 80-113 mA/mu m(2).

This work presents a novel Spacer-is-Dielectric (SID) SADP Ru semi-damascene integration scheme by using metal-based core and gap hard masks. More than 70% yield in tested line resistance and line-to-line leakage, especially in MP18 structures, confirm the flow feasibility. The tested MP18 structures show a median line resistance of, low line-to-line leakage at 1V, and breakdown voltages in the range of 12-14V.

This study highlights the effectiveness of a novel two-metal-level semi-damascene integration approach using fully self-aligned pillar-vias (FSAV) for interconnects ranging from 18 to 26 nm metal pitch. We employ EUV-SADP-SIM patterning scheme and direct metal etch of Ru to demonstrate the proof of concept on 300 mm wafers. This integration gives lower via resistance than the previously reported schemes and promises lower capacitance. Furthermore, it significantly widens the via litho and etch process window, making it more attractive for advanced semiconductor manufacturing.

Superconducting Digital (SCD) is a promising alternative to conventional complementary metal-oxide semiconductor (CMOS) technology, enabling high-speed and energy-efficient computing for Artificial Intelligence (AI) and High-Performance Computing (HPC). Here, we report the fabrication of three device modules that are the core building blocks for scalable SCD technology: 1) NbTiN BEOL interconnects, 2) NbTiN/aSi/NbTiN Josephson junctions (JJs), and 3) NbTiN/HZO/NbTiN tunable Metal-Insulator-Metal (MIM) capacitors. Material characterization and electrical measurements demonstrate high-quality superconducting devices with critical dimensions (CDs) down to 50 nm. NbTiN interconnects have critical temperature $T_{c} > 13\mathrm{K}$ and high critical current density $J_{c} > 120\text{mA}/\mu \mathrm{m}^{2}$, amorphous Si $\alpha$ Si) based JJs have $J_{C} > 0.8\text{mA}/\mu \mathrm{m}^{2}$, with a $I_{C}R_{N}$ of $\sim 1.1\text{mV}$. The tunable HZO MIM capacitors have high specific capacitance $C_{f}$ of ∼28 fF/μm2 and k-value of 30. All devices were fabricated on 300 mm wafers within thermal budget of 420 $^\circ\mathrm{C}$ using fabrication processes compatible with standard CMOS technology, representing many firsts, hence bridging the gap from feasibility studies to industrial fabrication.

High-aspect ratio (HAR-6-8) bottom Ru metal lines (M2), at CDs 7-10 nm and metal pitch (MP) 18-26 nm, in a two-metal level Ru semi-damascene interconnect configuration with fully self-aligned via (FSAV) is reported for the first time. M2 is patterned using EUV-SADP and subsequent direct-metal-etch (DME) of Ru film. At critical dimension (CD) of 10 nm, the resistance (R) of Ru line at AR6, measures at 235 Ω/μm which is 75% lower than the simulated Cu line R at AR2. The R yield of Ru lines across 300 mm wafer is >90% for MP20-26 nm. The FSAV R is competitive; vias landing on AR6 lines show a median R~33Ω with bottom CD of 8.5x12.3 nm 2 . Good quality of HAR Ru line interfaces is indicated by thermal shock tests showing no change in line R post 1000 h of thermal cycling between -50°C to 125°C.

Nb x Ti (1-x) N is a promising alternative to replace conventional Nb in superconducting devices. In this work, short loop devices with metal lines and vias were fabricated in IMEC 300-mm pilot line using direct metal etch, semi-damascene approach. Single line resistance of Nb x Ti (1-x) N wires show that >95% of devices meet the expected resistance of <5000 Ω/μm and leakage measurements show that >95% of devices have low leakage of <1E–16 A/ μm. Low temperature measurements show that the Nb x Ti (1-x) N wires have transition temperature of 12.5K within 0.5K that of thin film and a critical current of 0.15 mA, within 2X of theoretical maximum.

We present the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects varying 26 to 18nm metal pitch, using an EUV-based SADP scheme and subsequent direct etch of Ru, manufactured on 300mm wafers. The integration flow uses the subtractive etching principle of Ru on two subsequent metal levels. Single via resistance landing on 18nm pitch Ru lines shows that > 85% of the devices meet the target of <50Ω. Furthermore, the via chain offers a yield of 60% with a resistance close to the target of ~5k Ω. Besides, we show good uniformity and high VBD via-to-line with MP20 to MP26, establishing FSAV.