For the first time, we demonstrate a monolithic three-dimensional (M3D)-integrated 4K electrochemical random-access memory (ECRAM) array with sub-100 nm channels, fabricated atop of the Si-CMOS logic circuits using a back-end-of-line (BEOL)-compatible process (<= 200 degrees C). These devices exhibit significantly low device-to-device variation (sigma/mu similar to 0.026), along with outstanding endurance (5x10(6) pulses). By scaling channel dimensions down to 100 nm through electron-beam lithography, we attain a remarkable 100-fold improvement in programming speed. Full array-level analysis reveals that our proposed M3D-integrated ECRAM-based processing-in-memory (M3D-ECPIM) chip achieves 100% yield and exhibits highly uniform analog switching behavior across the entire 4K array. Additionally, the first chip-level evaluation of symmetry point and half-bias selectivity confirms that both meet the stringent specifications required for neural network training. Finally, the M3D-ECPIM chip demonstrates excellent pattern programming accuracy with only 0.05% error.
Although many pundits have forecasted the growth of edge AI device demand would far surpass the cloud [1] it has not happened yet. AI is widely used in the edge already, but the key killer applications have not evolved. The progress on cloud AI was enabled by AI acceleration with massively parallel compute and high bandwidth access to the memory. On the other hand, the edge device systems are more complex. Four key attributes of the consumer-oriented edge devices are low power consumption, robust connectivity, low cost and large manufacturing scale and these attributes make the edge AI implementations very challenging. Elegant integration and system level optimization of the core compute, AI acceleration, memory access, connectivity, sensing and power delivery blocks are key for edge devices to excel in each of these attributes. This talk will elucidate both the opportunities in front of the community to squeeze more from scaling/power reduction and the need to extend the bandwidth improvements from recent years into the edge devices to achieve the optimal edge system.
We introduce a phase-change memory (PCM) device architecture tailored for analog in-memory computing (AIMC). By confining the active, switchable volume to a compact disc-shaped geometry, this design enables a continuum of non-volatile states programmable at ultra-low currents and power (similar to 40 mu A/mu W), even in standard undoped Ge2Sb2Te5 (GST). Furthermore, the device exhibits a resistance window spanning over three orders of magnitude, while achieving higher overall resistance.
In this work, a DNA synthesis biochip with 256 x 256 resolution fabricated by using indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) technology is presented. A TFT-based gate-on-array (GOA) is also integrated to provide addressing capability for active-matrix driving of 65K pixels. The implemented biochip demonstrated high-throughput synthesis of high- quality oligonucleotides, ranging from 20 to 150 nucleotides in length at femtomole quantities, with optimization of electrode design and driving schemes. The platform maintains compatibility with standard TFT manufacturing processes while eliminating the need for complex photochemical control systems inherent to conventional approaches. This work paves the way for cost-effective, large-scale biochip fabrication, with potential applications in synthetic biology.
Industrial foundry processing of semiconductor spin qubits has revolutionized the scale and yield of quantum processors fabrication, which in turn enables the use of data-driven process optimization and device screening. This requires high-throughput electrical characterization at cryogenic temperatures with complex measurement protocols. Here, we present an investigation of the performance of SiMOS based spin qubit devices made in an optimized 300mm process flow. We showcase how the qubit device uniformity allows efficient characterization using a die-scale cryogenic prober at an effective electron temperature (T-e,T-eff) of 0.8 +/- 0.2 K, which is below the temperature threshold for high-fidelity qubit operation. We leverage machine learning for autotuning the devices and extract key metrics for charge sensor and quantum dot performance for 16 double-dot devices. Our results enable further process optimization as well as variability-aware design of larger SiMOS spin qubit processors.
The demand for compact, efficient and agile power amplifiers (PAs) continues to rise. GaN-on-Si technologies are anticipated to deliver PAs with superior power performance and smaller form factors. However, their typically high operating voltages are often incompatible with the power control units in current handsets. In this work, we demonstrate a GaN-on-Si low-voltage HEMT technology achieving a peak power-added efficiency (PAE) of over 80% and a saturated output power (P-out) of 2.84 W/mm at drain voltages <= 10 V at 2.2 GHz. A microwave monolithic integrated circuit (MMIC) featured as a three-stage PA based on our GaN-on-Si technology is successfully implemented in real handset applications for the first time and its system-level power performance is evaluated on the mainboard of a smartphone. At 2.0 GHz, the MMIC achieves a gain of 37.3 dB, a P-out of 38 dBm, and a PAE of 51.4% with required linearity (error vector magnitude < 5%) for efficient handset operation. These outstanding device- and circuit-level power performance surpass those of other technologies for LV RF applications, strongly indicating the potential of GaN-on-Si RF technologies for the next-generation efficient mobile communication systems.
We discuss device technologies for future optical circuit switches focusing on data center networks and machine learning supercomputers. Device parameters including insertion loss, crosstalk, port count, reconfiguration time, and polarization sensitivity can affect the final system performance and reliability.
We propose a real-time, all-RRAM intelligent gas perception (RIGP) system, featuring three cross-layer innovations. At the process level, a novel direct atomic layer processing (DALP) technique eliminates lithography and etching, enabling high-quality TiO2 deposition with variable thicknesses at designated locations. At the device level, a vertical TiO2-based gas sensor, built using a standard RRAM structure, exhibits high H2 responsivity. Its self-rectifying behavior effectively suppresses sneak current paths in high-density passive arrays without transistors. At the architecture level, the RRAM gas sensor enables seamless integration with an RRAM-based in-memory computing (IMC) platform. Variable TiO2 thicknesses facilitate local feature extraction within the sensor array, eliminating the need for analog-to-digital converters (ADCs). The RIGP system, incorporating hardware-encrypted acceleration of reservoir computing (RC), achieves highly accurate real-time detection (NRMSE < 0.08) and inherent security in a compact, energy-efficient design.
This paper presents an ultra-high-speed (UHS) global shutter burst CMOS image sensor (CIS) featuring pixel-wise analog memory arrays. The developed CIS with 628(H) x 480(V) pixels achieves a maximum frame rate of 20 Mfps and a readout speed of 6.03 Tpixel/s. A recording length of 256 frames and a parasitic light sensitivity (PLS) of -170 dB were also achieved simultaneously in a UHS camera. This low PLS is achieved through comprehensive metal shielding of the pixel circuit and memory regions, and by the spatial separation between the photodiode and memory regions, implemented using Si trench capacitors. The introduced bias adjustment circuit compensates for voltage variations among pixel positions due to the ground resistance and pixel circuit current during the pixel driving period, enabling high-resolution video recording with an effective 628(H) x 480(V) pixels and a 48 mu m pitch.
We demonstrate a ferroelectric NAND (FeNAND) cell featuring an engineered InGaZnO (IGZO) charge trap layer (CTL) for reliable 3D integration. To overcome endurance degradation and severe memory window (MW) loss during retention in conventional metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) gate stacks, we propose a metal-G.IL-oxide semiconductor (OS)-FE-Ch.IL-Si (MISFIS) structure incorporating a 2 nm-thick IGZO CTL. The IGZO CTL simultaneously serves as an oxygen reservoir to suppress oxygen vacancy (VO) formation in the FE layer and provides an energy band offset to reduce charge loss. In-situ N2 doping is applied to tailor the trap profile, achieving deep-level dominant traps at a 2 sccm flow rate. This optimized design enables a wide MW of 9.4 V with a low operation voltage (VOP) below 17 V, stable triple-level cell (TLC) retention over 10 years, and robust endurance exceeding 80k program/erase (PGM/ERS) cycles. These results validate the MISFIS FeNAND as a promising architecture for next-generation 3D FE memories.
In this work, we present comprehensive experimental and modeling studies addressing the challenges of our previously proposed dual-port ferroelectric FET (FeFET) architecture for pass disturb-free vertical NAND storage. This architecture incorporates a string-compatible independent pass gate within the string core, which is dedicated for pass operation rather than relying on the same write gate. Our key findings are as follows: i) The non-ferroelectric pass gate ensures pass disturb immunity via its geometry—pass voltage aids retention of the high-threshold voltage (HVT) state, while the its adverse influence on the low-threshold voltage (LVT) state is effectively screened by the channel; ii) A critical challenge is the increased leakage current in the HVT state, attributed to a weak back-channel region not fully depleted by the front gate, which is verified via both TCAD modeling and experimental demonstration; iii) To mitigate this, we explore the design space of the pass gate oxide and channel thickness through TCAD simulations, and experimentally validate the modeling using dual-port gate-side injection (GSI) FeFETs; iv) The example design, when implemented, demonstrates pass disturb-free operation while effectively managing the leakage trade-off; v) Another challenge is reduced ON-current for LVT state when unselected cells remain in HVT states. This can be mitigated by applying proper pass gate biases.
Two-dimensional (2D) semiconductors offer great promise for ultimate transistor scaling, with significant progress already demonstrated in n-FETs based on MoS2. However, high-performance p-type 2D transistors under aggressive pitch scaling remain insufficiently explored. In this work, we systematically investigate ultra-scaled monolayer WSe2 p-type transistors, achieving full-dimensional scaling of channel length, width, and contact length. A record contact pitch of 53 nm is demonstrated, with L-C=20 nm and L-CH=33 nm. The scaled device with a 100 nm channel width exhibits a high on-current of 350 mu A/mu m at V-ds=-1 V. Meanwhile, devices with a contact length of 200 nm achieve a lower contact resistance (R-C) of 0.61 k Omega center dot mu m and an on-current exceeding 1195 mu A/mu m at V-ds=-1 V. This work indicates the tremendous potential of WSe2 p-type transistors for ultra-scaled CMOS technologies.
This work reports on equivalent oxide thickness (EOT)-scaled MoS2 channel direct-grown two-dimensional (2D) field-effect transistors (FETs). We introduce a robust device fabrication process that integrates an oxide passivation step to utilize direct-grown 2D channels. The new process scheme enables nearly 100% device yield on 200 mm wafers for direct-grown 2D FETs and clean contact areas. From directly grown devices, we achieve lower interface defect states (D-it) than transferred devices, reducing device variation. Moreover, we engineer the crystal structure of the gate dielectrics using Al-doped HfO2 (HfAlO) and ZrO2 as substrates during direct MoS2 growth. By optimizing the device fabrication process and dielectrics, we achieve the highest reported on-current (I-ON) of 820 mu A/mu m at EOT of 1.15 nm among direct-grown 2D FETs.
This study demonstrates a gate interfacial layer (GIL) engineered vertical Gate-All-Around (GAA) 3D ferroelectric NAND (FeNAND) device that achieves a wide memory window of similar to 12 V at sub-15 V programming voltage. This marks a 4.4 V reduction compared to previous results, while achieving record retention and endurance, setting a new benchmark in FeNAND performance. We present the first experimental evaluation of read disturb (RD) and cell-to-cell interference (C2C) in FeNAND at scaled word line (WL) pitch, with direct benchmarking against charge trap NAND. The observed increases in RD (3x) and C2C (7x) are attributed to design trade-offs made to achieve the wider memory window, including thinner channel interlayers and gate-side charge injection operation. TCAD simulations reveal that electric field crowding at WL corners induces localized dipole flipping, intensifying C2C interference. These challenges can be mitigated through advanced gate stack engineering, optimized geometries as demonstrated in simulation, and alternative biasing schemes. These findings underscore critical design considerations for enabling scalable, low-voltage FeNAND integration in future 3D NAND architectures.
In this work, we push lightweight XOR-based in-situ encryption to extreme density by proposing a single-transistor XOR memory cell and applying it to 3D NAND, enabling secure data storage without density loss. Using a ferroelectric field-effect transistor (FeFET) as an example technology, we demonstrate that: i) a single-transistor memory can realize the XOR function by exploiting the ability to charge the source and drain separately and control current flow direction, eliminating the need for conventional encrypted cells that rely on complementary devices; ii) with a XOR-based cipher, encryption and decryption can be mapped to in-situ array operations, where ciphertext is stored as the threshold voltage (V-TH) states of FeFETs in a NAND string, and decryption is achieved through read operations using key-dependent complementary source/drain bias; iii) the proposed technique is scalable to multi-level cell (MLC) storage by encrypting and decrypting data bit by bit; iv) using an integrated NAND FeFET array, we experimentally demonstrate encryption and decryption operations for both single-level cell (SLC) and MLC storage; v) system-level benchmarking shows that the proposed technique achieves 48x and 278x improvements in encryption and decryption throughput, respectively, compared to AES.
a selective gate epitaxy strategy is proposed for p-GaN gate formation in enhancement- mode HEMTs to enhance robustness against hot- electron effects. This approach avoids p-GaN growth and etching processes in the access region, preserving the high-quality as-grown barrier layer. Compared to the conventional p-GaN gate HEMTs, devices with selective epitaxial gate demonstrate 1.5x higher drain breakdown voltage at VGS of 6 V and significantly reduced on-resistance degradation during long-term semi-on stress with V-DS ranging from 100 V to 400 V. The selective p-GaN gate epitaxy is also compatible with the gate recess process, maintaining normally-off operation with thick AlGaN barriers, achieving further on-resistance reduction.
We demonstrate a 300mm process for 2 types of SiMOS quantum dot spin qubit device architectures enabled by EUV lithography. First, we show an overlapping gates process for spin qubits, where the gates are fabricated for the first time using 0.33NA EUV lithography. We report excellent reproducibility, full wafer room temperature functionality and good quantum dot and qubit metrics at 10mK. Second, to enable qubit scalability, we demonstrate a single-layer gate device architecture fabricated with 0.33NA EUV patterning of the gate, and 2 damascene EUV BEOL layers.
For the first time, we experimentally demonstrate a monolithic 3D (M3D) integrated Hf0.5Zr0.5O2 ( HZO)-based 2TnF ferroelectric gain cell (Fe-GC), featuring vertical transistors and stackable storage nodes (SNs) for parallel operations. A co-designed parallel read computing-in- memory (CIM) scheme is proposed, aiming to accelerate the attention mechanism in Transformer. The write transistor employs self-oxidized tantalum (Ta) gate to form its gate oxide, while the read transistor showcases a vertical-top-gate IGZO FeFET with quasi-destructive read capability for the frequently accessed K matrix in attention. Utilizing the same ferroelectric film, high-density multi-bit SNs constructed on the sidewalls enable efficient one-time buffering of high-volume Q matrices. This co-optimization achieves high throughput and reduced read cost by minimizing data movement for dynamic matrix-vector multiplication (MVM). Array- level characterizations validate the proper function of 2TnF Fe-GC, highlighting its potential as a high-throughput KV cache for M3D integration. Performance benchmarks indicate a 13.0x overall performance improvement over conventional planar DRAM architectures.
Digital-to-Optical Converters (DOCs) convert digital electrical signals directly to analog optical signals, eliminating the need for Digital-to-Analog Converters (DACs) in Electro-Optic (EO) modulators, for more energy-efficient communication. Unfortunately, state-of-the-art DOCs suffer from either: (a) High non-linearity in transmitted optical power vs. input digital code (quantified by Integral Non-Linearity and Differential Non-Linearity). High INL & DNL degrade trade-offs in power, bandwidth, and Bit Error Rate. (b) High input signal count: previous Engineered Segment Length (ESL) DOCs improve INL & DNL, but require thermometer-coded digital input signals: N - 1 inputs for N-level Pulse-Amplitude Modulation (PAM-N). N - 1 inputs require N - 1 electronic drivers, increasing overall power consumption. Here, we present ESL*, a design technique enabling DOCs to achieve near-zero INL & DNL with only log(2)(N) inputs. Compared to thermometer-coded ESL-DOCs, ESL*-DOCs reduce power of electronic drivers by 3.82 x for PAM-16. We fabricate ESL*-DOCs in Lithium Niobate, implementing PAM-16. Compared to non-ESL-DOCs with log(2)(N) inputs, we measure 3.7 x better INL & 2.1 x better DNL.
Most trapped-ion quantum computers confine ions using precise voltages applied to electrodes and manipulate their internal states and execute quantum logic operations using focused laser beams. The prevailing approach to scaling these systems from current sizes that use tens of ions to ones with several orders of magnitude more ions relies on the lithographic fabrication of larger electrode arrays as well as on-chip integrated waveguides for delivering light to each individual ion. This approach solves the crosstalk problem that is inherent to free-space light delivery, but it does not address the input/output problem associated with coupling many optical signals to the on-chip waveguides. Here we describe an approach that uses CMOS-compatible optical modulators that can substantially address this challenge, and analyze its architectural implications.
