We present two wafer backside-frontside connection schemes for backside power delivery networks: (1) buried power rail combined with self-aligned nanoscale TSV, with ~250 nm of remaining Si substrate; (2) through dielectric via without remaining Si substrate. Integration flows of these two schemes are detailed. Different thinning approaches are compared. Intensive electrical and thermal characterizations have been done, including resistance, capacitance and heating rate (temperature increase as a function of applied power). It is exhibited that the remaining 250 nm Si substrate can reduce the heating rate of no remaining Si scheme from 100 K/mW to 50 K/mW. Meanwhile, a solid consistency between measurement and simulation has been achieved, in terms of both capacitance and heating rate characterizations.

Through silicon vias (TSVs) are key enablers of the next generation of microelectronic products. TSVs are holes through the silicon substrate, filled with a metal, forming vertical conductors between the backside and the frontside of the die. In the last 10 years, TSV dimensions have been strongly decreased, and their diameters are now reaching sub-micrometer dimensions, with aspect ratios just below 10. In this article, multiple sources of reliability concerns will be reviewed. First of all, the reliability of the liner/barrier system will be addressed. The difficulty to obtain full sidewall coverage, due to high aspect ratios, small via diameters or etch topography, and its impact on reliability will be demonstrated. Furthermore, the need to optimize the etch recipe to avoid copper sputtering leading to poisoning of the liner will be clarified. Finally, the electromigration performance of the TSVs will be discussed.

In this work, a predictive simulation of the nano-TSV to BPR connection process was performed that included realistic process effects. Resistance performance was explored to provide design guidelines and to optimize the RC performance of nTSV-BPR connection. Simulation results were also benchmarked against electrical measurements. This type of study can be used to provide Keep out Zone (KoZ) guidelines for TSV integration.

This paper highlights the advantages of 3D System-on-Chip (SoC) but also shows that system-technology co-optimization (STCO) will be required for system-level benefits. A physical design study was performed evaluating the design feasibility when multi-threading CPUs. The study shows that 250nm 3D pitches can enable this performance benefit without area penalties. To achieve this, two high density 3D interconnect technology enablers are described. For wafer-to-wafer Cu-SiCN hybrid bonding technology the challenges are outlined to enable scaling down the interconnect pitch from 300nm down to 200nm. Nano Through-Silicon Via (nTSV) technology enables fine-pitch 210nm and 120nm vertical connections between the frontside and backside of a wafer through extreme wafer thinning and overlay control in backside lithography.

A wafer to wafer hybrid bonding technology is realized featuring a hybrid interconnect pitch scaling down to 300 nm. Integration challenges and optimizations are extensively discussed. High electrical yield on large daisy chain structures is demonstrated.

Testing of spin-based quantum devices is currently performed through quantum dot and qubit measurements at deep cryogenic temperatures, well below 1 K. At such low temperatures, the testing throughput is strongly limited due to the long cool-down times and due to the large number of connections required between the device at deep-cryogenic temperature and the room-temperature control electronics. As the number of qubits in a single chip increases and as we advance toward large-scale manufacturing, developing effective techniques that allow to screen those chips at higher temperatures, possibly even room temperature, becomes indispensable. Transistor metrics constitute a promising indicator to identify, at room temperature, which devices are functional and also at cryogenic temperatures. Prior work has demonstrated a strong correlation between quantum dot metrics measured at deep-cryogenic temperature and transistor metrics up to 77 K. To ensure that such a correlation extends up to room temperature, electrostatic confinement of the conductive channel needs to be guaranteed. In this article, we propose a single-electron transistor (SET) design intended for the correlation study of transistor metrics from deep-cryogenic up to room temperatures. Our calibrated technology computer-aided design (TCAD) simulation results demonstrate the drastic improvement of the room-temperature transistor behavior of the proposed design, without the employment of physical device isolation that would negatively impact the qubit’s fidelity. In addition, this work presents a room-temperature-aware methodology in the design phase of spin-based devices, with promising scalability to structures containing a larger number of qubits.

Electron-spin qubits are among the most promising platforms for the realization of a large-scale quantum computer. Physical limitations dictate their operation at cryogenic temperatures, in practice often well below 1 K. This requirement implies the employment of a refrigerator featuring long cooldown times and the need for die packaging, thereby strongly limiting the number of devices that can be measured simultaneously. In our work, we evaluate traditional transistor metrics to enable fast wafer-level screening of electron-spin qubit devices above cryogenic temperatures. To the best of our knowledge, a clear link between quantum dot metrics measured below 2 K and traditional transistor metrics measured at higher temperatures has not yet been identified. In this paper, we study the correlation between 10 mK measurements in the few-electron regime, and traditional transistor metrics at different temperatures. We observe a strong correlation up to 77 K, while correlations at higher temperatures are much less pronounced. We analyze this poor correlation via room-temperature TCAD simulations, showing that the underlying physics changes due to a considerable contribution of the substrate current to the device’s off current above 77 K.

Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si $_{\text{0.75}}$ Ge $_{\text{0.25}}$ etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.

This study presents groundbreaking outcomes of 400nm pitch wafer-to-wafer (W2W) hybrid bonding connections with a Cu/SiCN bonding interface. A new test vehicle is introduced and meticulously designed for the relevant process development and studies. To ensure a precise surface topography control after CMP, a hexagonal pad grid is adopted, with dummy pads strategically placed in the unused layout areas. The design contains a large range of pad pitches from 1000nm to 400nm, accommodating both equal and unequal pad size configurations. Improved underlayer topography control emerges as a significant factor in achieving void-free bonding. Furthermore, the measured electrical data demonstrates close alignment with simulated models, encompassing resistance and capacitance. The impact of local pad-to-pad overlay error on the electrical properties of hybrid bond pads are also explored in this paper. The findings confirm the necessity for a maximum vector overlay tolerance of 100nm for 400nm pitch connections.

In this work, 0.7 mu m via-last TSV arrays were pre-stressed with a series of ten 60 V ESD pulses. Their liner reliability performances were subsequently investigated though voltage ramp stresses with various ramp rates to assess the impact of the ESD pre-stress on the dielectric properties. The breakdown voltage and leakage current of pre-stressed structures is unaffected by the ESD events.

This work explores the advancements and challenges in 3D IC stacking. Unlike traditional 2D planar ICs, 3D stacking vertically integrates multiple layers of circuits, offering improved performance, efficiency, and miniaturization. While this technology has been widely adopted for memory devices, it is less widely used for logic applications because of the challenges of stacking more than two dies. This study investigates the technological challenges and the impact of microbumps, hybrid bonding pads, and TSV pitch scaling on die-to-die interconnect performance. Results indicate that reducing interconnection pitch enhances data rate, bandwidth density, delay, and energy efficiency. Various stacking configurations and interconnection pitches are examined, showing promising results. Advanced stacking technologies like hybrid bonding mitigate performance gaps between 2 and 16 die stacks. Additionally, the study evaluates one-to-one and one-to-many interconnect links, revealing negligible differences in performance. Overall, this research provides insights into optimizing 3D IC stacking for enhanced circuit performance and capacity.

The reliability of an Al-doped HfO2 dielectric used in a high density 2.5D MIMCAP is investigated by constant voltage stress (CVS) and voltage ramp stress (VRS) measurements. The good agreement of the results from the two techniques allows to propose a model for lifetime prediction based on the breakdown characteristics. The extracted activation energy shows a voltage dependence associated with a change in the degradation characteristics of the high-κ material at high fields.

This paper presents an investigation into the scaling of wafer-to-wafer (W2W) hybrid bonding (HB) technology for the manufacture of advanced electronic devices. However, the scaling of W2W bonding has been challenging due to limitations in bond strength and alignment accuracy. In this study, we review the current state of W2W bonding technology and discuss recent breakthroughs that have enabled significant scaling. We propose a test vehicle design using a hexagonal grid with circular pads to overcome bonding overlay control challenges. We also explore the selection of SiCN as the bonding dielectric and demonstrate high bonding energy and controlled Cu bulge out. The results show successful control of Cu/SiCN surface topography, precise alignment accuracy, and favorable electrical performance. Additionally, we analyze the relationship between bonding overlay and single contact resistance, yield performance, and reliability. Our findings provide valuable insights into the advancements and significance of W2W bonding scaling.

Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a 3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.

This paper evaluates the impact of backside power delivery on the physical implementation of a commercial 64-bit high-performance block from ARM™ at the A14 node. A backside BEOL, including TSV connections, is proposed and calibrated using TCAD and experimental data. The developed stack is modeled in a commercial cell-level parasitic extraction tool to enable its use during place and route. The same benchmark is physically implemented using imec’s own A14 PDK. The backside PDN enables frequency improvements from 2% to 6% compared to frontside PDN, stemming from a core area reduction from 8% to 16%. These results are obtained without negatively impacting the total power and simultaneously limiting dynamic IR drop below 35mV. Furthermore, different TSV options have been studied to potentially boost the IR drop gains up to 23%.

Electron-spin qubits in silicon are one of the most promising platforms for implementing large-scale quantum computing. In this platform, a qubit, i.e., the basic unit of quantum information, is associated with the spin of a single electron confined in a region of silicon called a quantum dot. Electron-spin qubit devices must be operated at the cryogenic temperature of 40mK in a 3He/ 4 He dilution refrigerator. This requirement results in long cool-down (“soak”) times and increased costs, which slow down the technology development. Our research aims at developing a high-volume, room-temperature screening technique to assess quantum dots variability and select suitable candidates for mK measurements. In this paper, we present transistor measurement data of quantum dots across a 300mm wafer at temperatures ranging from 300K down to 225K. We analyze the statistical distributions of transistor metrics to detect outliers across temperatures, and hence to prevent wasting measurement time and resources at mK on known bad devices. From the collected data, we conclude that among the metrics analyzed, the threshold voltage appears to be the preferred metric for an effective pre-screening of silicon quantum dots.

Decoupling signal and power delivery routing to the transistors can be achieved by moving the power wiring to the wafer backside while signal routing is kept in the traditional BEOL of the wafer frontside. This novel concept is gaining a lot of traction to achieve enhanced signal integrity and high quality power delivery performance, and is becoming key for enabling higher gains from further scaling at transistor level while maintaining power savings. To improve the on-chip power delivery, a back-side power delivery network (BSPDN) with nano-through-silicon vias (nano-TSV) directly landing on buried power rails (BPR) of the standard cells has been developed. This novel approach requires extreme wafer thinning to less than 500nm final Si thickness with extremely good thickness control. The nano-TSV are processed from the wafer backside with better than 10nm alignment accuracy to the buried rails, enabling very high-density electrical connections between the backside and frontside of the device wafer. The nano-TSV and buried rail resistances have been characterized for various metallization options including low-resistivity metals as W, Co and Ru, and the manufacturing process has been optimized to reduce the contact resistance between the nano-TSV and the buried rails; measurement results are in good agreement with simulation data.

In this paper, backside power delivery network (BS-PDN) and a high density 2.5D Mimcap (Metal-insulator-metal capacitor) are applied to improve dynamic IR-drop of 2D and 3D ICs at a sub-2nm node. An on-chip PDN design and IR drop modelling framework is proposed and calibrated with the physical design results of 64-bit low power CPU. The calibrated framework is applied to 2D IC PDN with various Mimcap integration and then to 3D IC PDN. The 2.5D Mimcap used here was manufactured with optimized capacitance density of ~70 fF/um 2 . The BSPDN using 2.5D Mimcap has 32.1%/23.5% improvement in IR drop over the no Mimcap/2D Mimcap counterparts respectively, and BSPDN shows 36.3% improvement over the front side PDN (FSPDN) counterpart. Furthermore, by using 2.5D Mimcap + BSPDN in the 3D-IC, the top logic die IR drop is improved by 21.7%.

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also contacting directly the device’s S/D-epi. As for gate wiring, to enable in this work its access from both wafer sides, gate is also connected to BPR via V0 landing on it and on a neighboring M0A line set only on field-oxide. A single-step metallization for M0A and VBPR is preceded by in situ preclean(s) optimized for improved BPR-VBPR contact interface and ${R}_{\text {ext}}$ , as confirmed electrically and by physical analysis. After FS processing, wafer flipping, bonding, and extreme thinning, highly scaled, ~323 nm deep nano-through-Si-vias (nTSVs) land on BPR, with tight overlay control and unchanged BPR resistance [26%–29% lower with improved tungsten (W)-fill], connecting them to the first backside (BS) metal level (BSM1). By moving the power delivery network to the BS (BSPDN), besides alleviating FS routing congestion, considerably smaller dynamic and static IR drop values are predicted from on- chip power heat maps generated for a low power 64-bit CPU at 2-nm design rules: 82% and 96% less worst-case values versus a reference configuration, respectively. P/NMOS show similar or even superior ${I}_{ \mathrm{\scriptscriptstyle ON}}$ – ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ after BS processing and extra anneal(s) added for ${V}_{T}$ recovery, mobility and bias temperature instability (BTI) improvement—up to 8%/15% higher ${I}_{ \mathrm{\scriptscriptstyle ON}}$ linked to anneal selection.