In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

In this paper a new interconnect capacitance measurement method with a sub-attoFarad (<10/sup -18/ F) resolution is presented. We have developed a SPD (Single Pattern Driver) which allows to obtain directly all the coupling terms for a system of several interconnect electrodes. A very good fit is obtained between measurements and simulation for a state-of-the-art 0.18 /spl mu/m CMOS process with low-k. Moreover, we demonstrate that this SPD can be used for process characterisation and monitoring, and extraction tool validation.

In this paper, a new method (ARPIC: automatic representation of patterns for interconnect characterization) of interconnect capacitance characterization is shown. ARPIC is a matrix of 1606 patterns containing the most frequent capacitive loads existing in a design. Its main purpose is to calibrate a simulator. A very good fit is obtained between measurements and simulation for a state-of-the-art 0.18 /spl mu/m CMOS process with low-k dielectric, and we demonstrate that the ARPIC method can characterize interconnect capacitance with 0.1 fF resolution.