In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni2Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxides

In this paper, we show that Totally SIlicided (TOSI) gate electrodes offer an interesting and industrially viable option for the integration of metal gate electrodes in advanced CMOS technologies as their integration requires only few modifications with respect to a CMOS standard flow. Moreover, the use of NiSi gives access to an electrode with a tunable mid-gap work function. The potential of TOSI-gate devices is demonstrated by integration and device results including fully operational SRAM cells and reliability data.

This paper presents a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492muA/mum at Ioff: 25nA/mum @ Vdd -1.2V) despite the relatively thick gate oxide thickness used. The inverters' functionality of the FDSOI SRAM cell with a size of 0.99mum2 has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond

Introduction In order to fully evaluate a future technological choice, single device performance is not enough. Indeed in order to monitor the power consumption (e.g. SRAM leakage); speed of a “realworld” circuit (e.g. loaded circuits), and impact of process dispersion on circuit functionality, a System-Level performance evaluation becomes mandatory. In one hand, the generation of device model for design applications is well known and can be achieved by calibrating full SPICE models on early-silicon data, or by extrapolating models from a technological generation to another. In the other hand, because the fitting parameters are numerous, this approach is extremely time consuming, and difficult to apply to a large range of possible solution (i.e. device architecture change). We propose here a way to rapidly generate pre-sets of data using the MASTAR model, used for the definition of the ITRS Roadmap 2005.This tool can be used by device engineers to be able to get an early evaluation of their devices in circuits, including worst-cases study (dispersion). We will show in a first part that MASTAR model can reproduce silicon data on numerous parameters. In a second part, extrapolation possibility is demonstrated, and finally the example of process dispersion impact evaluation on SRAM cell functionality is given.

Conventional bulk CMOS scaling starts to fail. In order to prolong the life of Moore's laws, at least one technological booster (innovation) per node has to be introduced starting from the node 32nm on. This presents a big technological challenge for the semiconductor industry. On the other hand, accumulation of the boosters permits to retrieve healthy scaling down to sub-10nm gate lengths. This strategy even if technologically very challenging, is prospected to prolong the CMOS competitiveness till at least 2020.

Gate and drain current noise investigations are performed on nMOS transistors with HfO2 gate oxides. The drain noise magnitude allows extraction of the slow oxide trap density Nt(EF) ranging from 3 to 7 1019 eV−1 cm−3. These values are about 50 times higher than for SiO2 dielectrics. The 1/f gate current noise component is a quadratic function of the gate leakage current. The gate noise parameter KGC is about 2 10−17 m2, whereas, for SiO2 dielectrics this gate noise figure of merit is about 10−19 m2.

In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications

We present in this paper a detailed analysis of the electrical behaviour of NMOS transistors with gate lengths down to Lg = 30nm where the source/drain extensions (SDE) were developed using ultra low energy implantation (As 1keV) or plasma doping (PLAD) at low bias (1.5kV). PLAD splits show excellent threshold characteristics in comparison with As 1keV: delayed Vt roll-down, reduced Short Channel Effect (SCE) and Drain Induced Barrier Lowering (DIBL). The Ion/Ioff trade-off analysis reveals a much lower Ioff for comparable gate lengths when using PLAD instead of ULE. These behaviours are explained by a reduced junction depth Xj, which is confirmed by a parameter extraction on transistor characteristics and by analytical modelling.

In this paper, we present electrical results on damascene CMOS devices containing a HfO/sub 2/ gate oxide and a TiN/W gate electrode and give a detailed analysis of the performance data and the carrier mobility in both pMOS and nMOS devices. We report on an improvement of the electron mobility compared to recent literature data, which seems to be related to a slightly higher interfacial oxide layer. These findings are very interesting regarding the definition of a good trade-off between mobility and EOT for future CMOS transistors using high-k materials for the gate oxide.

In this paper, we evaluate new concepts in the ultra shallow junction engineering such as Ultra Low Energy (ULE) and Plasma Doping Implant (PLAD) and fast ramp-up Spike Annealing after integration into planar 60nm-transistors. Excellent results in terms of SCE and DIBL reduction are obtained for As implant at 1 keV and B PLAD implant for nMOS and pMOS devices respectively. Further improvement can be obtained by using Levitor Spike Annealing. Future work has to be focussed on the optimisation of the transistor performances.