Many consumer products used daily contain sensors and image sensors (smartphones, cars, automated tools, etc.). There is a growing demand to enhance the capabilities of industrial products to probe their environment more efficiently, i.e., under difficult conditions (smoke, darkness, etc.). One solution is to extend the capabilities of image sensors to detect light toward the near-infrared and short-wave infrared (SWIR) regions. Because silicon has weak absorption properties in the infrared, especially in the SWIR region, manufacturers are investigating the use of new materials to build these sensors. To this end, colloidal quantum dot (QD) thin films made from the assembly of PbS nanoparticles have emerged as promising materials. They offer tunable bandgaps, favorable absorption properties, and scalability in production. However, patterning the active parts of photodiodes by plasma etching of this new material presents challenges. The etching chemistry must be selected to volatilize Pb and S without modifying the unetched active part of the PbS QD photodiode, and the etching profile should be anisotropic. In this study, we have screened several plasma operating conditions (power, pressure, and temperature) in various chemistries (H2, Cl2, HBr, and N2). To understand the etch mechanisms and profiles, ToF-SIMS and TEM/energy dispersive x-ray were employed. Our findings reveal that halogen-based plasmas cause QD material deterioration through Cl or Br diffusion deep in the film. While H2 plasmas are efficient to etch PbS QD films, they result in high roughness due to the removal of the carbonated ligands that separate PbS QDs. This ligand etching is followed by QD coalescence leading to significant roughness. However, the addition of N2 to H2 can prevent this phenomenon by forming a diffusion barrier at the surface, resulting in favorable etching characteristics.

Ge‐rich Ge–Sb–Te (GGST) alloys are the most promising materials for phase‐change memory in embedded applications, being able to fulfill the tough data retention requirements of automotive and consumer markets. GGST alloys are sensitive to thermal budgets and spatial confinement; thus, memory device process integration and architecture can strongly impact their final electrical properties and reliability. Herein, exploiting a statistical methodology capable to extract quantitative metrics for evaluating by‐process segregation, the inhomogeneity of out‐of‐fab GGST material in function of process parameters is studied such as architecture and alloy composition. The present results with the already known source of segregation, namely the back‐end‐of‐line thermal budget, are compared providing a comprehensive description of the main modulating factors of segregation among these different process parameters.

After patterning of Phase Change Memory (PCM) stack, residues are growing after etching and air exposure. This kind of defect might lead to severe impacts on the devices performances and reliability. In this work, we study the modification of the Ge-GST surface after HBr-based plasma etching and air exposure. We evaluated the CH 4 -based in situ post etch plasma treatments as a solution to protect Ge-GST and prevent the formation of residues.

In phase-change random access memory (PCRAM) applications, the germanium antimony tellurium alloy (GST) is patterned using halogen etching in inductively coupled plasma reactors. This paper focuses on the surface state evolution of an optimized Ge-rich GST material after plasma etching. Four hours after etching, big dome-shaped residues are observed on PCRAM structures. Their number and size increase with the time of air exposure. X-ray photoelectron spectroscopy and energy-dispersive x-ray spectroscopy analyses reveal an important germanium oxidation on the surface with residues. Their formation is then investigated. Complementary analyses highlight that the moisture environment has a catalytic effect on the residue formation. Based on this study, a detailed mechanism responsible for residue formation is proposed.

We have developed a $1.62\mu \mathrm{m}$ pixel pitch global shutter sensor optimized for imaging in the near infrared (NIR) and shortwave infrared (SWIR) regions of the light spectrum. This breakthrough was made possible through the use of our colloidal Quantum Dot (QD) thin film technology, which we have named Quantum Film (QF). We have scaled up this new platform technology to our 300mm manufacturing toolset. The challenges associated with the introduction of solution-processed, colloidally grown lead sulfide (PbS) QDs in an industrial 300mm fab environment were successfully overcome. The QF photodiodes, leveraging either NIR or SWIR sensitive QDs, were optimized for high quantum efficiency (QE), low dark current and immunity to operating stress. Global shutter pixel arrays, with pixel pitch of $2.2\mu \mathrm{m}$ and $1.62\mu \mathrm{m}$ exhibit unprecedented QE of >50% and MTF @ Nyquist/2 of 0.75 and 0.6, respectively. The robustness of our 300mm Quantum Film technology was fully assessed and reliability in terms of meeting all required lifetime specifications for consumer electronics and other potential applications has been demonstrated.

The integration of new materials in the next generation of optoelectronic devices leads to several challenges. For instance, the etching of indium tin oxide (ITO, In2O3:Sn) faces the issue of the low volatility of In- and Sn-based etch products at room temperature. This is challenging for the etching process itself, but even more problematic when the inductively coupled plasma (ICP) reactor must be cleaned after etching: since the reactor walls are bombarded by low energy ions only, the removal of In- and Sn-based products redeposited on the walls can be very long and laborious. Therefore, we have investigated several plasma chemistries to find the most efficient reactor cleaning process suitable for ITO plasma etching. The results show that after ITO plasma etching the walls are indeed contaminated by indium. At the low temperature at which the reactor walls are regulated, BCl3/Cl-2 cleaning plasma is ineffective to remove this deposit while HBr and CH4/Cl-2 chemistries provide promising results.

This paper discusses an innovative architecture of charge storage NVM cell, which outpaces state-of-the-art in term of bit-cell area. This new concept of memory cell is used today in production for microcontrollers. After cell architecture and activation description, we will present process flow integration challenges, process optimizations and single cell characterizations.

The complexification of integrated circuit designs along with downscaling introduces new patterning challenges. In logic process integration, it is found that the gate etch process flow introduces a few nanometer displacement of the gate patterns from their original position fixed by the lithography layout. This phenomenon referred to gate shifting (GS) generates a contact to gate overlay misplacement that compromises the transistor electrical performance. HBr cure plasma, which is a well-established postlithography treatment to increase photoresist stability and improves both line edge roughness (LER) and critical dimension uniformity during pattern transfer, has been identified as the root cause of the gate shifting phenomenon. The vacuum ultraviolet (VUV) irradiation emitted by HBr plasma leads to an asymmetric flowing of the two-dimensional resist patterns, and thus to a displacement of the gate patterns. Based on plasma optical emission measurements, the HBr plasma conditions are optimized to limit the VUV irradiation. If the GS phenomenon can indeed be eliminated using low VUV dose HBr plasma conditions, it introduces some strong LER issue during the subsequent Si antireflective coating (Si ARC) fluorocarboned plasma process. Indeed, low VUV dose HBr cure plasma does not play anymore its hardening role. The elimination of the GS issue is a priority for the transistor electrical performance. The strategy adopted in this study is to remove the HBr cure treatment and to optimize the subsequent Si ARC etch plasma process to minimize LER degradation during this step. The developed SF6/CH2F2 Si ARC plasma etching process uses low energy ion bombardment combined with a fluorine rich chemistry to avoid the formation of a fluorocarbon polymer on the resist pattern, which is the main contributor for resist surface and sidewalls roughening. The new gate patterning process flow that is proposed in this article allows to eliminate the GS phenomenon but also to improve the final gate LER from 3.5 to 2.8 nm. Moreover, the study highlights the capability of the developed SF6/CH2F2 Si ARC plasma chemistry to address the most advanced nodes with even more aggressive gate dimensions by eliminating the wiggling phenomenon occurring with previous Si ARC plasma chemistries for gate dimension inferior to 25 nm.

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

The analysis of a same sample using nanometre or atomic-scale techniques is fundamental to fully understand device properties. This is especially true for the dopant distribution within last generation nano-transistors such as MOSFET or FINFETs. In this work, the spatial distribution of boron in a nano-transistor at the atomic scale has been investigated using a correlative approach combining electron and atom probe tomography. The distortions present in the reconstructed volume using atom probe tomography have been discussed by simulations of surface atoms using a cylindrical symmetry taking into account the evaporation fields. Electron tomography combined with correction of atomic density was used so that to correct image distortions observed in atom probe tomography reconstructions. These corrected atom probe tomography reconstructions then enable a detailed boron doping analysis of the device.

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma.It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc.) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1].In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate /poly-silicon /oxide hard mask stack.We will show that modifying the resist-cure /Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.

Planar Fully-Depleted (FD) Silicon On Insulator (SOI) MOSFET technology has already demonstrated large performance boost vs bulk at 28nm node (>30%) and is very competitive for incoming mobile & multimedia products thanks to design porting from bulk. Indeed, FDSOI is very attractive for low power applications due to its low sub threshold slope (~60mV/dec), better short channel effect (SCE) control and reduced junction capacitance. 28nm FDSOI devices highly depend on gate CD morphology because electrical effective gate length is driven by metal gate CD. High-k metal gate etching is therefore a key point to achieve these requirements. Gate profiles and metal gate CD control are mandatory and variability has to be minimized across the wafer (WiW), wafer to wafer and lot to lot. In this paper, we will focus on metal gate CD variability investigation. Once polysilicon gate profiles are frozen, metal gate profiles adjustment is achieved, based on scatterometry metal gate profiles measurements, TEM analysis and electrical results. Thanks to this methodology, a metal gate etching process has been tuned on 300mm industrial platform etcher. This work was performed at ST Crolles 300 facility in collaboration between STMicroelectronics & CEA/LETI.

In this paper, we compare the electrical properties of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) MOS devices for rotated and non-rotated substrate with different gate lengths. We found a significant performance enhancement on FDSOI PMOSFETs for rotated substrates as expected, while keeping a good control of short channel effects. Surprisingly, to a lower extent, an improvement is also found for NMOS devices. We have also studied the carrier mobility degradation as a function of temperature and we point out the contribution of different mechanisms that reduce the mobility such as impurity Coulomb scattering, phonons and neutral defects as a function of gate length. We find that there is no significant effect of rotated substrate on the mobility degradation at room temperature. All these results are discussed and possible explanations are also given. (C) 2013 Elsevier Ltd. All rights reserved.

Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch side we will have to control both polysilicon and metal gate CD’s. For device integration it will be extremely important to monitor N and PMOS devices and get appropriate gate profiles since transistor morphology is a key contributor to device performances. In parallel of CD control, thin silicon film on top of buried oxide layer will also require a strict control of its thickness. Scatterometry is the only way to get all these informations from a patterned environment [1]. We will show in this paper how scatterometry has been proven to be accurate enough to support the realization of DOE’s for metal gate profile optimisation at gate patterning without doing hundred’s of TEM. Scatterometry results are correlated to parametric tests and TEM for ultimate validation.

The present work focuses on the line width roughness (LWR) transfer and the critical dimension control during a typical gate stack patterning and shows the benefits of introducing 193 nm photoresist treatments before pattern transfer into the gate stack to improve process performance. The two investigated treatments (HBr plasma and vacuum ultra violet (VUV) plasma radiation) have been tested on both blanket photoresist films and resist patterns to highlight the etching and roughening mechanisms of cured resists. Both treatments reinforce the etch resistance of the photoresist exposed to fluorocarbon plasma etching process used to open the Si-ARC (silicon antireflective coating) layer. The etch resistance improvement of cured resists is attributed to both the decrease in oxygen content within the resist and the crosslinking phenomena caused by VUV radiation during the treatment. As the magnitude of the surface roughness is directly correlated to the etched thickness, cured resists, which are etched less rapidly, will develop a lower surface roughness for the same processing time compared to reference resists. The LWR evolution along the pattern sidewalls has been studied by critical dimension atomic force microscopy during the Si-ARC plasma etching step. The study shows that the LWR is degraded at the top of the resist pattern and propagates along the pattern sidewalls. However, as long as the degradation does not reach the interface between resist and Si-ARC, the LWR decreases during the Si-ARC etching step. As resist pretreatments reinforce the resist etch resistance during Si-ARC etching, the LWR degradation along the sidewalls is limited leading to minimized LWR transfer. The LWR decrease observed after plasma etching has been explained thanks to a spectral analysis of the LWR performed by critical dimension scanning electron microscopy combined with the power spectral density fitting method. The study shows that the high and medium frequency components of the roughness (periodicity below 200 nm) are not totally transferred during the gate patterning allowing a LWR decrease at each plasma step.

This work highlights the way to optimize the speed/power performance of the planar FDSOI technology at the 28nm node and beyond. The combination of gate length shrink and spacerO increase leads to 13% delay decrease and 15% dynamic power saving at same speed through capacitance reduction. It demonstrates that, as far as the access resistance penalty is kept reasonably low, increasing the spacerO is highly efficient to boost AC performance in FDSOI.

With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an accurate estimation of the CDSEM noise level and extraction of unbiased LWR.In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length, fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H-2, He, Ar), and also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H-2 that limit carbon redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

With the constant decrease of semiconductor device dimensions, line width roughness (LWR) becomes one of the most important sources of device variability and thus needs to be controlled below 2 nm for the future technological nodes of the semiconductor roadmap. The LWR control at the nanometer scale requires accurate measurements, which are inevitably impacted by the noise level of the equipment that causes bias from true LWR values. In this article, we compare the capability of two metrology tools, the critical dimension scanning electron microscopy (CD-SEM) and critical dimension atomic force microscopy (CD-AFM) to measure the true line width roughness of silicon and photoresist lines. For this purpose, we propose several methods based on previous works to estimate the noise level of those two equipments and thus extract the true LWR. One of the developed methods for the CD-SEM technique generalizes the power spectral densities (PSD) fitting method proposed by Hiraiwa and Nishida with a more universal autocorrelation function, which includes both correlation length and roughness exponent. However, PSD fitting method could not be used with CD-AFM due to the time consuming character of this technique. Hence, other experimental protocols have been set up for CD-AFM in order to accurately characterize the LWR. Our study shows that the CD-SEM technique combined with our PSD fitting method is much more powerful than CD-AFM to get all roughness information (true LWR, correlation length, and roughness exponent) with a good accuracy and efficiency on hard materials such as silicon. Concerning materials degradable under electron beam exposure such as photoresist, the choice is more disputable, since ultimately they are impacted by the electrons. Fortunately, our PSD fitting method allows working with low number of integration frames, which limits the resist degradation. Besides, we have highlighted some limitations of the CD-AFM technique due to the tip diameter. This technique can underestimate LWR if the roughness presents significant amount of high frequency components, as it is the case for photoresist patterns. So far, there is no universal technique to accurately estimate the LWR on any materials. Nevertheless, the CD-SEM protocol we propose opens a way for a better characterization of the photoresist LWR after lithography and a better understanding of the LWR transfer during the plasma etching steps involved in gate patterning processes.