An area of increasing interest for SiC device processing is the processing and qualification of silicon oxides. In this article a contactless corona CV (CnCV) measurement procedure is evaluated as a way to gain more knowledge about the different processes related to oxides. A 21-point measurement pattern is used to gain information about uniformity of oxide properties. Two different types of oxides have been considered, low pressure chemical vapor deposited (CVD) oxides using tetraethylorthosilicate (TEOS) and thermally grown oxides. The two different groups have received different combinations of pre- and post-processing steps prior to measurements. As expected, low pressure CVD (LPCVD) and thermally grown SiO 2 without any post oxidation annealing (POA) showed significantly different electrical characteristics compared to the wafers that did get a POA. This difference could clearly be distinguished by CnCV, meaning that individual process steps can be analyzed without the fabrication of any test structures on the wafers. As the individual process steps can be analyzed, the uniformity of the individual steps can be accessed. Using a 21-point pattern it was possible to show that there is a non-uniformity in the LPCVD process used prior to the POA. This makes the CnCV technique suitable for in-line characterization and process monitoring.

This paper compares ethene and methane precursors for homoepitaxial 4H-SiC growth in planetary reactors with regards to their impact on growth rate and defectivity of the epilayers. Therefore, a comprehensive experimental study has been performed in AIXTRON G10-SiC and G5WW C planetary reactors using a standard process based on ethene and trichlorosilane precursors with conventional 150 mm n-type 4H-SiC substrates from 3 different international suppliers. Methane substituted ethene as precursor in many experiments. It was found that methane precursor can compete with ethene in terms of growth rate, epilayer thickness, and defectivity of the epilayers. By using isotopically enriched methane, Si 12 C epilayers with a 12 C concentration of 99.96 % have been grown which can be used for SiC-based quantum technology.

Precise control of optical transitions of color centers like silicon vacancies (V Si ) in 4H-SiC is essential for their functionalization. An applied electric field (E || c) of a pin-diode can be used to tune the optical properties of V Si centers via the Stark effect, while the associated space charge region under bias suppresses spectral diffusion. Unlike commonly used 4H-SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes and resonant laser excitation of the V Si perpendicular to the wafer surface (a ⊥ c). In this work non-circular lateral pin-diodes oriented perpendicular to the wafer flat were produced in a scalable, CMOS-compatible process. Electrical characterization revealed that 97% of the devices on an a-plane wafer with n-type epitaxial layer were functional, exhibiting breakdown voltages exceeding 200 V and reverse currents below 100 pA/µm, enabling low current noise during optical measurements. The diodes remained operational at cryogenic temperatures after frozen-out charge carriers were re-ionized by the applied electric field. Electron irradiation followed by thermal annealing at 600 °C was used to generate V2 silicon vacancies in the intrinsic region without significantly altering the electrical characteristics. Optically detected magnetic resonance (ODMR) measurements on selected single emitters confirmed the presence of V2 centers by detecting a contrast at 70 MHz, while cryogenic photoluminescence (PL) spectra revealed a zero-phonon line (ZPL) peak at 916 nm.

The yield of power electronic devices is influenced by many factors including crystal defects like stacking faults (SFs). There are different types of stacking faults but their influence on the finished device and its performance and the behavior of SF during processing is not fully understood yet. With our contribution, we shed light on the issue, showing four different optically characterized subtypes of SFs with different electrical behavior that can already be found after implantation and wafer annealing in photoluminescence (UVPL) imaging. This enables a distinction between different SF classes without the need for a finally processed device and the corresponding electrical characterization. The goal of this paper is to illustrate an alternative for subdividing SF types that would otherwise be detected as triangular defects without any distinction and to show the different effects those subclasses have on finished devices with non-destructive methods that can be used in between device manufacturing steps. These results will be used as basis for further studies to confirm the found classes and to compare them with research about the different crystal structures by spectral PL measurements. For better understanding of the effect on the finished device, the PL imaging data is correlated with I-V characteristics of trenched diodes and the defect types are evaluated on their effect on the I-V characteristic, identifying 3 defect types with detrimental influence on the reverse bias and blocking voltage while the forward bias characteristic and I-V characteristic of one type is not effected by the defects.

The quality of the epitaxial layer plays an important role in the performance of modern power electronic devices. Minority carrier lifetime is known to be sensitive to defects like dislocations, stacking faults, and points defects. Therefore, in this work lifetime measurements by microwave detected photoconductivity decay are used to evaluate the quality of the epitaxial layer on various 4H-SiC substrates from different vendors. The stability of the measurement technique is shown by a daily release measurement. This allows for a reliable analysis of almost 300 typical 1,200 V epilayer stacks. It has been shown that the effective lifetime of these samples can be separated into two different ranges. The lifetime values of about 120 ns fit to theoretical calculations. The cause for the increased lifetime of about 250 ns in the second range has yet to be determined in further research. Furthermore, the lifetime maps were used to locate defects in the surface near regions.

Silicon vacancies (V Si ) are relevant for quantum technologies, including sensing, computing, and communication. For the realization of quantum photonic integrated circuits (QPICs) and, therefore, co-integration of optical and electrical devices with resonant excitation through the wafer surface, a-plane 4H-SiC wafers are required. Transferring established complementary metal-oxide-semiconductor (CMOS)-compatible processes from c-plane to a-plane wafers is, therefore, a crucial step. In this work, key fabrication steps, namely ion implantation, thermal oxidation, and ohmic contact formation, were investigated for a-plane 4H-SiC substrates. To demonstrate successful process transfer, p-channel MOS field-effect transistors were fabricated and electrically characterized, showing comparable I on /I off ratios and mobilities to their c-plane counterparts, but with a threshold voltage shift from −7.1 V to −12.0 V on the a-plane. Additionally, tunneling diodes were realized as broadband light emitters, with a significant portion of the emission spectrum falling within the range of off-resonant excitation of V Si centers. The devices maintained light emission functionality down to cryogenic temperatures.

Engineered SiC wafers with a thin 4H-SiC layer bonded on a polycrystalline carrier substrate for the application as substrate in epitaxy are investigated. Epitaxial layers grown on such substrates in 150 mm and 200 mm diameter are compared to those on state-of-the-art conventional substrates from different vendors. The performance of the engineered wafers is judged by doping and thickness uniformities as well as the number and statistics of killer defects in the epitaxial layer.

This study presents a novel approach to device yield estimation based on the non-contact, corona-based QUAD (Quality, Uniformity, and Defects) technique for inline defect mapping in SiC epitaxial layers. The approach is applied to a merged PiN Schottky (MPS) diode manufacturing process and is compared to final wafer-level electrical data. A new analysis method for QUAD defect mapping is introduced, incorporating die yield bin maps based on in-die depletion voltage values, allowing for a direct die to die comparison with standard EOL (End of the Line) electrical device testing. The QUAD mapping flow plan includes initial epi-wafers, the EOL wafers with measurement on metalized MPS dies, and the wafers after stripping off the metal. Micro-scale, $\mu $ QUAD depletion voltage maps resolving individual dies gives further insight into the nature of the device failures. Novel results show processing induced failures associated with defective electrical isolation of diodes. The unique yield-killing effects of clusters of stacking fault triangular defects are evidenced by a catastrophic breakdown voltage collapse and QUAD depletion voltage collapse in clusters of failed dies near the wafer edges. A strong correlation between the inline QUAD bin map results and final failed device maps highlights the potential of QUAD as a practical and powerful inline tool. This technique, achieving a 94% capture of failing MPS dies, offers a complementary approach to UVPL defect imaging, identifying electrical killer-defects and enhancing the yield estimations.

The crystal orientation of 4H-SiC a-plane (11-20) wafers allows efficient optical readout of silicon vacancies across the surface of the wafer. This sparks significant interest in utilizing a-plane wafers for quantum applications. Given the distinct properties of a-plane wafers compared to conventional c-plane (0001) wafers, well-established CMOS process steps require re-evaluation to ensure a fully functional CMOS process and comparable electrical properties. In epitaxial growth, the layer-by-layer growth on a-plane substrates leads to a smooth surface with a roughness of 0.08 nm. The incorporation of dopants is sevenfold increased, compared to c-plane substrates. For ion implantation on a-plane wafers, the 30° periodicity of (11-20) and (1-100) directions induces extended channeling, creating a 2D ion implantation profile with flanks in the ± 30° directions from the intended doping profile. For thermal oxidation a sixfold increased linear rate constant on a-plane wafers led to increased oxide growth rate in the reaction-limited regime.

A distributed quantum network would require quantum nodes capable of performing arbitrary quan-tum information protocols with high fidelity. So far the challenge has been in realizing such quantum nodes with features for scalable quantum computing. We show here that using the solid-state spins in 4H silicon carbide (4H SiC) such a goal could be realized, wherein a controlled generation of highly coher-ent qubit registers using nuclear spins is possible. Using a controlled isotope concentration and coherent control we perform here atomistic modeling of the central spin system formed by the electron spin of a silicon-vacancy color center (V-Si center) and the noninteracting nuclear spins. From this we lay out conditions for realizing a scalable nuclear-spin (13C or 29Si) register, wherein independent control of the qubits alongside their mutual controlled operations using the central electron spin associated to the V-Si center in 4H SiC are achieved. Further, the decoherence and entanglement analysis provided here could be used to evaluate the quantum volume of these nodes. Our results mark a clear route towards realizing scalable quantum memory nodes for applications in distributed quantum computing networks and further for quantum information protocols.

For the ongoing commercialization of power devices based on 4H-SiC, increasing the yield and improving the reliability of these devices is becoming more and more important. In this investigation, gate oxide on 4H-SiC was examined by time-zero dielectric breakdown (TZDB) and constant current stress (CCS) time-dependent dielectric breakdown (TDDB) method in order to get insights into the influence of the epitaxial defects on the gate oxide performance and reliability. For that purpose, MOS capacitors with different gate oxides have been fabricated. Crystal defects in the epitaxial layers have been detected and mapped by ultraviolet photoluminescence (UVPL) and interference contrast (DIC) imaging. The results of the comparison of electrical data and surface mapping data indicate a negative influence on the leakage current behavior for some extended epitaxial defects. Results from TDDB measurement indicated numerous extrinsic defects, which can be traced back to gate oxide processing conditions and defect densities.

The feasibility of thin 4H-SiC layers bonded on an alternative carrier substrate for the application as substrate in SiC epitaxy is investigated. Epitaxial layers grown on such substrates are compared to those on state-of-the-art conventional substrates from different sources. The performance of the substrates is judged by the occurrence of killer defects in the epitaxial layer as analyzed using a PL scanning tool. Additional investigations on the material properties were carried out using X-ray topography and Atomic Force Microscopy, yielding information on the crystallinity, the lattice curvature, and the surface properties of the epitaxial layers.

The minority carrier lifetime is a decisive factor to obtain 4H-SiC bipolar devices with a low forward voltage drop at high blocking voltages. The lifetime is directly correlated with the concentration of the so-called Z(1/2) deep level and depends on the epitaxial growth process and post-epi processing like ion implantation, annealing, and thermal oxidation. The substrate has so far been attributed a subordinate role for the minority carrier lifetime. In this work, the influence of substrate quality on the minority carrier lifetime after epitaxial growth and post-epi processing is studied on substrates from different manufacturers. The investigation revealed a significant impact of the substrate contamination on the minority carrier lifetime of epitaxial layers and on the efficiency of lifetime enhancement by thermal oxidation. A deep level named SD2 was found in the samples which acts as an additional Shockley-Read-Hall recombination center. The deep level SD2 was traced back to the substrates themselves showing different levels of incorporation of recombination sites from the substrate into the epitaxial layer during the growth. A comparison of the energy levels and electron capture cross sections of the SD2 deep level with defects caused by a tungsten contamination shows a good agreement.

This chapter summarizes and explains the key factors in the development of 4H-SiC homoepitaxial growth and defect engineering. It will be shown that 4H-SiC homoepitaxy is a mature technology today, based on step-flow growth on vicinal substrates in a CVD process, providing epilayers of high structural quality. Still, extended defects like such as e.g. dislocations, stacking faults, and complexes thereof as well as point defects are relevant for device performance and device production yield. This chapter classifies defects, explains their nature and occurrence, provides adequate strategies for defect avoidance, and introduces pertinent characterization methods for such defects. Special attention is paid to the physical properties of point defects and their impact on minority carrier lifetimes.

In this study, UV Photoluminescence (UVPL) and Differential Interference Contrast (DIC) mapping was applied for process control of a 1.2 kV 4H-SiC VDMOS fabrication process at different process stages in order to investigate the influence of shallow pits on the electrical behavior of the devices. In particular, it could be shown that UVPL and DIC mapping allows the correlation of shallow pits and the occurrence of darker regions in the UVPL images and distinguishing differently implanted regions at distinct process stages. By comparing the darker regions of the UVPL scan with the electrical blocking characteristics of the associated devices a direct correlation between the occurrence of shallow pits and the reduction of the blocking capability of the devices could be observed.

Lifetime-engineering in 4H-SiC is important to obtain a low forward voltage drop in bipolar devices with high blocking voltages above 10kV. It is known that the implantation of carbon and subsequent thermal annealing can be used to improve the minority carrier lifetime of as-grown epitaxial layers due to annihilation of carbon vacancies and, therefore, reduce the lifetime limiting defect Z 1 / 2. In this paper, the ion implantation of other ions (N, Al, B, and As) besides carbon and their impact on minority carrier lifetime and point defect concentration are shown. Special attention is paid to the effect of ion implantation with subsequent electrical activation by high temperature annealing. A strong influence of the implantation dose and, therefore, corresponding resulting doping concentration was found. A lifetime enhancement could be found for some implanted species for higher implantation doses whereas the detrimental effect of high temperature annealing dominated at low implantation doses. The results reveal that the implantation dose and the occupied lattice sites are important parameters to achieve a lifetime enhancement. A model is presented which explains the different impacts of various implanted ions and a more detailed understanding of lifetime-engineering by ion implantation. With this knowledge, it was possible to reduce the detrimental Z 1 / 2 defect in a large part of thick epitaxial layers with conventional shallow ion implantation and high temperature annealing. Consequently, the minority carrier lifetimes of the epitaxial layers could be enhanced.

Temperature dependent microwave detected photoconductivity MDP and time-resolved photoluminescence TRPL were employed to investigate the carrier lifetime in CVD grown 4H-SiC epilayers of different thickness. The minority carrier lifetime may be found from both theMDP and defect PL decay at room temperature for all epilayers, whereas the near bandedge emission (NBE) decay is much faster for thin epilayers (<17 μm) due to the substrate proximity and only follows the minority carrier lifetime for thicker samples at lower excess carrier concentrations.

Two fully loaded epitaxial growth runs with 16 wafers in total were conducted in the AIXTRON G5 WW reactor in order to keep epigrowth conditions constant. The wafers were selected with a large spread of specific resistivity and dislocation densities. The resulting epilayers showed very good intra-wafer homogeneities as well as excellent wafer-to-wafer and run-to-run reproducibility with regard to epilayer thickness and doping concentration, point defect concentrations of Z 1/2 and EH 6/7 and the resulting Shockley-Read-Hall carrier lifetime. We found that the dislocation densities of the underlying substrates are influencing the stacking fault densities of the epilayers, which then vary between 0.1 and 10 cm -2 . A substrate effect on the effective minority carrier lifetime was found.

Electrical testing with regard to bipolar degradation of high voltage SiC devices cannot be done on wafer level, but only expensively after module assembly. We show that 4H-SiC material can be optically stressed by applying high UV laser intensities, i.e. bipolar degradation as in electrical stress tests can be provoked on wafer level. Therefore, optical stressing can be used for control measurements and reliability testing. Different injection (=stress) levels have been used similar to the typical doping level of the base material and similar to the established electrical stress test. The analysis of degradation is done by photoluminescence imaging which is a well-established technique for revealing structural defects such as Basal Plane Dislocations (BPDs) and stacking faults (SFs) in 4H-SiC epiwafers and partially processed devices.