The compensation of charge carriers is an important aspect to be considered in Aluminum doped areas in 4H-SiC. In this paper, a straightforward method has been found to implement compensation effects into a basic device simulation model and to improve the conformance of electrical measurement and simulation results. By implementing the compensation factors, which depend on Aluminum doping concentration, device simulation in combination with basic device cell structure can be used to create electrical characteristics that are in accordance with measured characteristics. This is a simple alternative for complex process simulation, taking into account physical effects like defects in the crystal structure. The method was used for simulation of lateral MOSFETS transfer characteristic as well as VDMOS blocking characteristic. Found compensation values were 80 % in the 1.5 ∙ 10 17 cm - 3 Al-doped channel region and 23% in the deep, 7.5 ∙ 10 1 7 cm - 3 Al-doped, shielding region.

The electrical behavior of lateral 4H-SiC n-laterally-diffused metal-oxide semiconductor (LDMOS) transistors with reduced surface field (RESURF) for integrated circuits was designed, measured, and modeled using different design variations. An additional implanted n-layer forming the drift region of the device in a p-doped epitaxy promotes a RESURF and thereby enhances the breakdown capability. The design rules of the presented power MOSFET are compatible to an existing technology for a novel 20-V 4H-SiC CMOS process. The dose of the additionally implanted RESURF region with a depth of approximately 390 nm was 3.5 center dot 10(12) cm(-2). Breakdown voltages in the range of 372-981 V and ON-state resistances from 1000 down to 54 m Omega cm(2) were measured, depending on the design variations. The best measured figure-of-merit (FOM, V2BD/RON) value results in 12.3 MW/cm(2). Additionally, the electrical behavior of the presented n-LDMOS transistor was compared to a TCAD simulation model. Hereby, design guidelines concerning the length of the channel, drift region, and field plate were derived, which will be helpful for further investigations. Moreover, according to the simulations, a deeper RESURF region of 1 mu m and a higher RESURF dose of 6 center dot 10(12) cm(-2) would even result in FOM values above 43 MW/cm(2).

Lifetime-engineering in 4H-SiC is important to obtain a low forward voltage drop in bipolar devices with high blocking voltages above 10kV. It is known that the implantation of carbon and subsequent thermal annealing can be used to improve the minority carrier lifetime of as-grown epitaxial layers due to annihilation of carbon vacancies and, therefore, reduce the lifetime limiting defect Z 1 / 2. In this paper, the ion implantation of other ions (N, Al, B, and As) besides carbon and their impact on minority carrier lifetime and point defect concentration are shown. Special attention is paid to the effect of ion implantation with subsequent electrical activation by high temperature annealing. A strong influence of the implantation dose and, therefore, corresponding resulting doping concentration was found. A lifetime enhancement could be found for some implanted species for higher implantation doses whereas the detrimental effect of high temperature annealing dominated at low implantation doses. The results reveal that the implantation dose and the occupied lattice sites are important parameters to achieve a lifetime enhancement. A model is presented which explains the different impacts of various implanted ions and a more detailed understanding of lifetime-engineering by ion implantation. With this knowledge, it was possible to reduce the detrimental Z 1 / 2 defect in a large part of thick epitaxial layers with conventional shallow ion implantation and high temperature annealing. Consequently, the minority carrier lifetimes of the epitaxial layers could be enhanced.

In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm2 for a device with a RESURF structure with a total implanted Al concentration of 6∙1016 cm-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

The prediction of the compensation induced hole concentration reduction in implanted Al regions is a key parameter in developing high power SiC devices. Hall effect measurements are commonly used to determine the compensation ratio of Al implanted regions. Due to the fact that this measurement method is rather complex, an approximate method was developed by using transfer length method structure measurements in combination with a TCAD simulation model. The determined compensation ratios from this work’s simulation and from Hall effect measurements from literature show consistent compensation ratios. Based on this data a fit function was derived which allows for estimating the compensation ratio for a wide Al concentration range.

Aluminum implanted 4H-SiC often shows an unexpected increase of the free hole density at elevated temperatures in Hall Effect measurements. Here we show that this phenomenon cannot solely be traced down to the Hall scattering factor and the presence of excited acceptor states. It is necessary to assume an additional defect center in the lower half of the band gap with ionization energies higher than that of aluminum to explain this behavior. Therefore, we investigated ion-implanted square van-der-Pauw samples with Hall Effect and complementary SIMS measurements. An analysis of the data using the neutrality equation reveals compensation ratios of 20 % to 90 %, depending on the aluminum concentration and the concentration of the deep defect center of up to 50 % of the doping.

In 4H silicon carbide, aluminum implantation causes unusual high compensation ratios as obtained from Hall effect investigations by fitting the neutrality equation with a single acceptor. We show that this approach cannot fully describe the experimental data, in particular in case of moderate doping and at high measurement temperatures above 450 K. We develop two extended models by adding an additional acceptor- or donor-like defect to the equation. Both approaches describe the data well. However, it turns out that an additional aluminum-correlated acceptor is the more reasonable choice. In this case, the compensation ratio stays almost independent of the implantation dose between 30 % and 40 %. The deep acceptor is located at EV + (280–400) meV.

In this work, deep defects in an aluminum-implanted 4H-SiC n-type epitaxy are discussed in dependence on following influencing factors: concentration of implanted aluminum, implantation energy, implantation at 500°C and at room temperature, as well as ascending or descending order of implantation energies during ion implantation using Gaussian profiles. The compensation ratio, which reaches values up to 90% of the implanted aluminum concentration, is determined by Hall Effect measurements. Compensating defect centers (Z 1/2 -, ON x -defects) are detected by Deep Level Transient Spectroscopy after high energy ion implantation using an energy filter, followed by an annealing and an oxidation process.

In this work, we analyze compensating defects which are formed after implantation of aluminum (Al) into n-type 4H-SiC epitaxial layers and subsequent thermal annealing. These defects reduce the expected free charge carrier density by 84% for a low doped layer with [Al]impl≈ 9ž·1016cm-3and by 27 % for a high doped layer with [Al]impl≈ 2·ž1019cm-3. Furthermore, an electrical activation ratio of implanted aluminum ions of 100 % is calculated. The ionization energy of implanted aluminum as measured by Hall effect and admittance spectroscopy ranges from 101 meV to 305 meV depending on the doping concentration.

We report on the threshold voltage () instability under operating conditions after gate bias switches at constant drain voltage for n-MOSFETs fabricated on 4H silicon carbide (4H-SiC). This effect occurs at room temperature and close to the of the device. We show that the origin of the instability is electron trapping into SiO2 over an energy barrier of (0.3-0.4) eV. These traps show similarities to traps previously observed in 4H-SiC MOS capacitors and labelled near interface traps (NITs). Further, the density of the traps can be reduced by one order of magnitude through post-oxidation annealing in nitric oxide atmosphere.

Drain current DLTS (I D -DLTS) and Hall effect measurements were carried out on two types of 4H-SiC n-MOSFETs, one with a post oxidation annealing (POA) in NO and one in O 2 atmosphere. Hall effect measurements show a reduction of D it by POA in NO compared to POA in O 2 and, as a consequence, a higher inversion charge carrier density, while the Hall mobility is only weakly affected by the introduction of nitrogen during POA. Based on I D -DLTS we provide a method for a quantitative and selective investigation of near interface traps (NITs) in the oxide. It is shown that POA in NO strongly reduces the density of NITs.