Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- $V_{\textit {th}}$ transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and $V_{\textit {th}}$ , while the low- $V_{\textit {th}}$ transistors exhibit a larger change in off-state leakage current. The " worst-case" bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( $V_{\textit {gs}}=V_{\textit {dd}}$ ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- $V_{\textit {th}}$ transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

Ever since the introduction of the metal-oxide-silicon field-effect-transistor (MOSFET), the nature of mobile and trapped charge in the oxide layer has been studied in great detail. For example, contamination with alkali ions such as sodium, causing instability of the flat-band voltage, was a major concern in the early days of MOS fabrication. Another SiO2 impurity of particular interest is hydrogen, because of its beneficial property of passivating charge traps. In this work we show that annealing of Si/SiO2/Si structures in forming gas (Ar:H2; 95:5) above 400 °C can introduce mobile H+ ions into the SiO2 layer. These mobile protons are confined within the oxide layer, and their space-charge distribution is well controllable and easily rearrangeable by applying a gate bias, making them potentially useful for application in a reliable nonvolatile MOSFET memory device. We present speed, retention, endurance, and radiation tolerance data showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as Flash. The chemical kinetics of mobile-proton reactions in the SiO2 film are also analyzed in greater detail. Our data show that the initial buildup of mobile protons during hydrogen annealing is limited by the rate of lateral hydrogen diffusion into the buried SiO2 films. The final density of mobile protons is determined by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temperature of the final anneal. To explain the observations, we propose a dynamical equilibrium model. Based on these insights, the incorporation of the proton generation process into standard semiconductor process flows is discussed.

The radiation response of lateral power MOSFETs in total dose and energetic particle environments is explored. Results indicate that lateral power MOSFETs can be quite susceptible to single-event burnout. Tradeoffs involved in developing radiation hardened lateral power MOSFETs for point-of-load applications are studied using experiments and device simulations. Both design and fabrication process techniques can be used to significantly improve the single-event effect performance of lateral power MOSFETs, but the trade space between electrical and radiation performance must be carefully considered to produce an optimized design for point-of-load applications.

A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A “tool set” of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

We have demonstrated a simple technique for building n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and complex micromechanical systems simultaneously instead of serially, allowing a more straightforward integration of complete systems. The fabrication sequence uses few additional process steps and only one additional masking layer compared with a microelectromechanical system (MEMS)-only technology, but exposes the MOSFET gate oxide to the extreme temperatures of MEMS processing. We find that the high-temperature MEMS anneals can greatly change the current-voltage characteristics of the SiO2 gate oxide film. Defects are introduced by the high-temperature processing which result in considerable positive-charge trapping at short times that leads to increased currents using high bias fields and short bias times. At longer times, the current across the oxide decays as 1/time suggesting electron traps that are uniformly distributed in the bulk of the oxide. A traditional reliability evaluation of the thick oxides using time-dependent dielectric breakdown is greatly hampered by excessive impact ionization that occurs at high gate voltages. This makes a rigorous evaluation of gate oxide lifetime at use fields difficult. We do note that while the current below breakdown is altered by the positive-charge trapping, the voltages at breakdown seen in ramps are not severely impacted by the high-temperature annealing. Breakdown voltages of films annealed at the highest of the temperatures studied here are about the same as those of unannealed films. The breakdown fields of these stressed oxides are 10–11MV∕cm, suggesting that reliable SUMMiT™ field-effect transistor process gate oxides can be fabricated as long as the use voltage is well below the onset for impact ionization.

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO2) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

We have demonstrated a simple technique for building n-channel metal-oxide-semiconductor-field effect transistors (MOSFETs) and complex microelectromechanical systems (MEMS) simultaneously, instead of serially, allowing a more straightforward integration of complete systems. The fabrication sequence uses few additional process steps and only one additional masking layer compared to a MEMS-only technology, but uses processes outside the bounds of conventional complementary metal-oxide-semiconductor very large-scale integrated devices. The process flow forms the MOSFET gate electrode using the first level of mechanical polycrystalline silicon (polysilicon), while the MOSFET source and drain regions are formed by dopant diffusions into the substrate from subsequent levels of heavily doped polysilicon that are used for mechanical elements. We have observed that phosphorus-doped gate polysilicon shows negligible dopant diffusion through the gate oxide during high-temperature MEMS processing anneals, whereas arsenic-doped gate polysilicon shows significant diffusion through the oxide. We have adapted a commercial process and device simulator to model a wide range of device designs and process flows.

Under conditions that were predicted as "safe" by well-established TCAD packages, radiation hardness can still be significantly degraded by a few lucky arsenic ions reaching the gate oxide during self-aligned CMOS source/drain ion implantation. The most likely explanation is that both oxide traps and interface traps are created when ions penetrate and damage the gate oxide after channeling or traveling along polysilicon grain boundaries during the implantation process.

Implanting the buried oxide of silicon-on-insulator technologies can create electron traps throughout the buried oxide that can compensate the buildup of radiation-induced positive charge. These can be used as an effective method for total-dose hardening buried oxides in SOI devices. In this work, we show that implanting buried oxides can also create thermally activated metastable electron traps near the top Si/SiO2 border. These metastable electron traps can produce significant bias instabilities in the back-gate transistor characteristics and lead to threshold voltage instabilities in fully-depleted devices.