Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

Passive silicon photonic waveguides are exposed to gamma radiation to understand how the performance of silicon photonic integrated circuits is affected in harsh environments such as space or high energy physics experiments. The propagation loss and group index of the mode guided by these waveguides is characterized by implementing a phase sensitive swept-wavelength interferometric method. We find that the propagation loss associated with each waveguide geometry explored in this study slightly increases at absorbed doses of up to 100 krad (Si). The measured change in group index associated with the same waveguide geometries is negligibly changed after exposure. Additionally, we show that the post-exposure degradation of these waveguides can be improved through heat treatment.

Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy deposition (MRED) approach is used to identify potential single-event susceptibilities associated with different layouts prior to fabrication. MRED is also applied to bound single-event testing responses of standard and dual interlocked cell latch designs. Heavy ion single-event testing results validate new latch designs and demonstrate bounds for standard latch layouts.

In this paper, we test Si vertical-junction disk modulators and waveguide-integrated Ge p-i-n photodiodes (PDs) to see how the key performance metrics are affected by Co-60 gamma radiation (total ionizing dose), a common proxy for simulating a mix of high-energy ion particle flux. It is found that reverse bias dark current increases significantly for both devices after 1-Mrad(Si) exposure. As the bandwidth of the Si disk modulator decreases by 6.5% after 1-Mrad(Si) dose, the bandwidth of the Ge p-i-n PD appears to be unaffected. The increased sensitivity of the Si disk modulator bandwidth to gamma radiation is hypothesized to be caused by a decrease in the carrier concentration of the junction with a resulting increase in the p-n junction RC time constant. The Ge p-i-n PD is relatively insensitive to the surface effects, because the absorption happens away from the SiO2-Ge interface and the gamma radiation has a minimal effect on carrier mobility.

The effect of a linear accelerator's (LINAC's) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are investigated. The data indicate that the photocurrent response of Si-based RF bipolar junction transistors and RF p-i-n diodes is considerably higher when taking into account the microstructure effects. Similarly, the response of diamond, SiO 2 , and GaAs photoconductive detectors (standard radiation diagnostics) is higher when taking into account the microstructure. This has obvious hardness assurance implications when assessing the transient response of devices because the measured photocurrent and dose rate levels could be underestimated if microstructure effects are not captured. Indeed, the rate the energy is deposited in a material during the microstructure peaks is much higher than the filtered rate which is traditionally measured. In addition, photocurrent models developed with filtered LINAC data may be inherently inaccurate if a device is able to respond to the microstructure.

In this work, experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The upset cross-sections were obtained with accelerated testing using both protons and heavy ions. The proton upset cross-sections were obtained using proton energies ranging from 1 to 500 MeV and the heavy ion data were obtained using ions with effective linear energy transfer (LET) values from 0.6 to 100 . Overall, the SBU data on the 45 nm SOI SRAM showed upset cross-sections-per-bit that were very similar to the cross-sections-per-bit on a 65 nm SOI SRAM for both heavy ion and proton testing. This result continues a trend that has been observed with advanced SOI CMOS SRAMs. In contrast to the SBU data, the MBU data on the 45 nm SRAM showed significantly higher upset cross-sections relative to the 65 nm SRAM. The higher MBU cross-sections were also expected based upon the closer spacing of the nodes in adjacent cells. While the overall trends were anticipated, the major focus of the paper was to understand a diverse range of single event effects that were contributing to the measured upsets. As a function of the incident proton energy, both scattering events and direct ionization upsets were observed. The data also highlighted the unique upset results that are produced at a 90 degree tilt angle. The MBU data showed a very large dependence on the data stored in the SRAM. The data dependence was understood based upon the layout of the SRAM cells and the MBU upsets produced by strikes in common diffusion regions. A detailed analysis of the MBU data showed that almost all of the MBU events occurred in adjacent cells along the bit-lines of the array. This result is very important since the MBU events along the same bit-line will be effectively corrected by error-correctingcode (ECC) circuits. Thus, the higher overall MBU cross-sections that were observed with technology scaling are not a critical issue in SOI SRAMs that use ECC circuits. David F. Heidel received his B.S. degree in physics from Miami University in 1974, and his M.S. and Ph.D. degrees in physics from The Ohio State University in 1976 and 1980 respectively. In 1980, he joined IBM’s Research Division, at the Thomas J. Watson Research Center in Yorktown Heights, NY, working on Josephson superconducting technology. Since

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.

We present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.

The locations of conductive regions in TaOx memristors are spatially mapped using a microbeam and Nanoimplanter by rastering an ion beam across each device while monitoring its resistance. Microbeam irradiation with 800 keV Si ions revealed multiple sensitive regions along the edges of the bottom electrode. The rest of the active device area was found to be insensitive to the ion beam. Nanoimplanter irradiation with 200 keV Si ions demonstrated the ability to more accurately map the size of a sensitive area with a beam spot size of 40 nm by 40 nm. Isolated single spot sensitive regions and a larger sensitive region that extends approximately 300 nm were observed.

TaOx and TiO2 memristors have been irradiated with 800 keV Ta ions, 28 MeV Si ions, and 10 keV X-rays. TaOx devices were also irradiated with 70 keV electrons. Displacement damage effects are studied using 800 keV Ta ions and both technologies show changes in resistance for fluences greater than 1010 cm-2. TaOx devices show gradual resistance degradation in the off-state with increasing fluence. TiO2 devices show gradual inconsistent increases in off-state resistance with inconsistent abrupt decreases. TaOx devices show more stability and consistent off-state resistances than TiO2 devices. Ionization effects are investigated using 28 MeV Si ions, 70 keV electrons, and 10 keV X-rays. During 28 MeV Si irradiation, both technologies change from the off-state to the on-state when a critical ionizing dose is reached without applying voltage or current to the device. The critical threshold is calculated using SRIM to be on the order of 60 Mrad(Si) or higher. 10 keV X-ray irradiation of doses up to 18 Mrad(Si) per step show little effect on either technology. A single TaOx device irradiated with 70 keV electrons changed from the offstate to the on-state at a calculated dose on the order of 100 krad(Si), suggesting a difference in charge yield compared to the 28 MeV Si irradiation.

The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam. For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. We show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

The effects of radiation on memristors created using tantalum oxide and titanium oxide are compared. Both technologies show changes in resistance when exposed to 800 keV Ta ion irradiation at fluences above 10(10) cm(-2). TaOx memristors show a gradual reduction in resistance at high fluences whereas TiO2 memristors show gradual increases in resistance with inconsistent decreases. After irradiation TaOx devices remain fully functional and can even recover resistance with repeated switching. TiO2 devices are more variable and exhibit significant increases and decreases in resistance when switching after irradiation. Irradiation with 28 MeV Si ions causes both technologies to switch from the off-state to the on-state when ionizing doses on the order of 60 Mrad(Si) or greater (as calculated by SRIM) are reached without applying current or voltage to the part. Irradiation with 10 keV X-rays up to doses of 18 Mrad(Si) in a single step show little effect on either technology. TaOx and TiO2 memristors both show high tolerance for displacement damage and ionization damage and are promising candidates for future radiation-hardened non-volatile memory applications.

This document gives detailed test guidelines for single-event upset (SEU), single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) hardness assurance testing. It includes guidelines for both heavy-ion and proton environments. The guidelines are based on many years of testing at remote site facilities and our present understanding of the mechanisms for single-event effects.

This document describes the radiation environments, physical mechanisms, and test philosophies that underpin radiation hardness assurance test methodologies. The natural space radiation environment is presented, including the contributions of both trapped and transient particles. The effects of shielding on radiation environments are briefly discussed. Laboratory radiation sources used to simulate radiation environments are covered, including how to choose appropriate sources to mimic environments of interest. The fundamental interactions of radiation with materials via direct and indirect ionization are summarized. Some general test considerations are covered, followed by in-depth discussions of physical mechanisms and issues for total dose and single-event effects testing. The purpose of this document is to describe why the test protocols we use are constructed the way they are. In other words, to answer the question: "Why do we test it that way"?

The effects of ionizing radiation and displacement damage on TaO x memristors are evaluated. Devices show little response to 10 keV x-rays up to 10 Mrad(Si). Co 60 gamma rays and 4.5 MeV protons did not change the resistances significantly at levels up to 2.5 Mrad(Si) and 5 Mrad(Si) respectively. 105 MeV and 480 MeV protons cause switching of the memristors from high to low resistance states in some cases, but do not exhibit a consistent degradation. 800 keV silicon ions are observed to cause resistance degradation, with an inverse dependence of resistance on oxygen vacancy density. Variation between different devices appears to be a key factor in determining the electrical response resulting from irradiation. The proposed degradation mechanism likely involves the creation of oxygen vacancies, but a better fundamental understanding of switching is needed before a definitive understanding of radiation degradation can be achieved.

Physical mechanisms of single-event effects that result in multiple-node charge collection or charge sharing are reviewed and summarized. A historical overview of observed circuit responses is given that concentrates mainly on memory circuits. Memory devices with single-node upset mechanisms are shown to exhibit multiple cell upsets, and spatially redundant logic latches are shown to upset when charge is collected on multiple circuit nodes in the latch. Impacts on characterizing these effects in models and ground-based testing are presented. The impact of multiple-node charge collection on soft error rate prediction is also presented and shows that full circuit prediction is not yet well understood. Finally, gaps in research and potential future impacts are identified.