Dual junction GaInP/GaAs solar cells have been grown and fabricated on Si substrates using relaxed, compositionally graded SiGe buffer layers that provide a nearly lattice-matched low threading dislocation Ge surface for subsequent cell growth. The dual junction cells on SiGe/Si displayed high open circuit voltages in excess of 2.2 V, compared to 2.34 V for control cells on GaAs, that are consistent with maintaining the 1.8/spl times/10/sup 6/ cm/sup -2/ threading dislocation density throughout the cell structure. Even with total current output limited by large grid coverage and high reflectance, total area AM1.5G efficiency is 16.8%, with active area efficiency at 18.6%. The high V/sub oc/ establishes that SiGe metamorphic buffers are viable for integrating III-V multijunction cells on Si in a monolithic process.

The effect of 2MeV proton radiation on the introduction of deep levels in GaAs grown on compositionally graded SiGe∕Si substrates was investigated using deep level transient spectroscopy (DLTS). Systematic comparisons were made with identical layers grown on both GaAs and Ge substrates to directly assess the influence of threading dislocations on radiation-related deep levels for both n-type and p-type GaAs. DLTS revealed that for p+n structures, proton irradiation generates electron traps at Ec−0.14eV, Ec−0.25eV, Ec−0.54eV, and Ec−0.72eV in the n-GaAs base, and, for n+p structures, radiation-induced hole traps appear at Ev+0.18eV, Ev+0.23eV, Ev+0.27eV, and Ev+0.77eV in the p-type GaAs base, irrespective of substrate choice for both polarities. The primary influence of substituting SiGe∕Si substrates for conventional GaAs and Ge substrates is on the introduction rates of the individual traps as a function of proton radiation fluence. Substantially reduced concentrations are found for each radiation-induced hole trap observed in p-type GaAs, as well as for the Ec−0.54eV trap in n-GaAs for samples on SiGe∕Si, as a function of proton fluence. Calculated trap introduction rates reveal reductions by as much as ∼40% for certain hole traps in p-GaAs grown on SiGe∕Si. This increased radiation tolerance for GaAs grown on SiGe∕Si is attributed to interactions between the low density (∼106cm−2) of residual dislocations within the metamorphic GaAs∕SiGe∕Si structure and the radiation-induced point defects. Nevertheless, the fact that the impact of dislocations on radiation tolerance is far more dramatic for n+p GaAs structures compared to p+n structures, may have implications on future III-V∕Si space solar cell design optimization, since end-of-life versus beginning-of-life differences are critical factors for power profiling in high radiation environments.

High-performance p(+) /n GaAs solar cells were grown and processed on compositionally graded Ge-Si1-xGex-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm(2) solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AMO) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm(2) did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.

GaAs on Si (GaAs/Si) solar cells grown on Si substrates coated with a step graded buffer of Si/sub x/Ge/sub 1-x/ alloys graded to 100% Ge have demonstrated AM0 efficiencies in excess of 17%. Recently, 4 cm/sup 2/ devices were developed in preparation for on-orbit testing aboard Materials International Space Station Experiment number 5 (MISSES). In preparation for flight, thermal cycling life testing and thermal shock testing have been conducted to examine the stability of these thermal coefficient of expansion mismatched structures. Six thousand (6000) thermal cycles, equivalent to one year in LEO, from -80/spl deg/C to +80/spl deg/C have been completed with no discernable degradation in the electrical performance. The use of metamorphic III-V materials, of larger lattice parameter, has demonstrated the ability to dramatically reduce the micro crack density, presumably through strain balancing. Recently, the first demonstration of metamorphic tandem devices (1.6 eV InGaP / 1.1 eV InGaAs) on Si substrates was accomplished. The devices appeared micro crack free as determined by Nomarski optical microscopic examination and electroluminescence image analysis. Thermal shock testing of GaAs/Si devices showed micro crack formation and device electrical degradation. Thermal cycle testing of metamorphic structures (InGaP/InGaAs/Si) demonstrated a general lack of micro crack formation and improved thermal stability compared to GaAs/Si control devices.

Dual junction (DJ) In/sub 0.49/Ga/sub 0.51/P/GaAs solar cells were grown on compositionally graded Ge/Se/sub 1-x/Ge/sub x//Si (SiGe), fabricated and characterized. The DJ solar cells exhibited open-circuit voltage (V/sub OC/) values in excess of 2 V for both AM0 and AM1.5 illumination. The high V/sub OC/ values result from maintaining very low defect densities in these highly lattice-mismatched structures by using SiGe graded layers and monolayer-scale control over the III-V/Ge interface formation. Comparisons made with identical cells grown on GaAs substrates reveal that the DJ solar cell on SiGe retained 91% of the V/sub OC/ and 99% of the short circuit current density achieved by the homoepitaxial DJ cell, demonstrating the potential for high efficiency multi-junction solar cells grown on SiGe. In addition, modeling shows that In/sub 0.49/Ga/sub 0.51/P/GaAs DJ cells should be more tolerant of the low residual dislocation densities characteristic of lattice-engineered SiGe substrates than single junction GaAs cells, indicating great promise for achieving a high efficiency III-V multijunction cell technology on Si.

The monolithic integration of high efficiency III-V compound solar cell materials and devices with lower-cost, robust and scaleable Si substrates has been a driving force in photovoltaics (PV) basic research for decades. Recent advances in controlling mismatch-induced defects that result from structural and chemical differences between III-V solar cell materials and Si using a combination of SiGe interlayers and monolayer-scale control of III-V/IV interfaces, have led to a series of fundamental advances at the material and device levels, which establish that the great potential of III-V/Si PV is within reach. These include demonstrations of GaAs epitaxial layers on Si that are anti-phase domain-free with verified dislocation densities at or below 1×106 cm−2 and negligible interface diffusion, minority carrier lifetimes for GaAs on Si in excess of 10 ns, single junction GaAs-based solar cells on Si with open circuit voltages (Voc) in excess of 980 mV, efficiencies beyond 18%, and area-independent PV characteristics up to at least 4 cm2. These advances are attributed in large part to the use of a novel “engineered Si substrate” based on compositionally-graded SiGe buffers such that a high-quality, low defect density, relaxed, “virtual” Ge substrate could be developed that can support lattice-matched III-V epitaxy and thus merge III-V technology based on the GaAs (or Ge) lattice constant with Si wafers. This paper focuses on recent results that extend this work to the first demonstration of high performance III-V dual junction solar cells on SiGe/Si. Open circuit voltages in excess of 2 V at one-sun have been obtained for the conventionally “lattice-matched” In0.49Ga0.51P/GaAs dual junction cells on inactive, engineered SiGe/Si; to our knowledge is the first demonstration of > 2V solar power generation on a Si wafer. Comparisons with identical cells on GaAs substrates reveal that the Voc on engineered Si retains more than 94% of its homoepitaxial value, and that at present both DJ/GaAs and DJ/SiGe/Si cells are similarly limited by current mismatch in these early cells, and not fundamental defect factors associated with the engineered Si substrates.

Recent experimental measurements have shown that in GaAs with elevated threading dislocation densities (TDDs) the electron lifetime is much lower than the hole lifetime [C. L. Andre, J. J. Boeckl, D. M. Wilt, A. J. Pitera, M. L. Lee, E. A. Fitzgerald, B. M. Keyes, and S. A. Ringel, Appl. Phys. Lett. 84, 3884 (2004)]. This lower electron lifetime suggests an increase in depletion region recombination and thus in the reverse saturation current (J0 for an n+∕p diode compared with a p+∕n diode at a given TDD. To confirm this, GaAs diodes of both polarities were grown on compositionally graded Ge∕Si1−xGex∕Si (SiGe) substrates with a TDD of 1×106cm−2. It is shown that the ratio of measured J0 values is consistent with the inverse ratio of the expected lifetimes. Using a TDD-dependent lifetime in solar cell current–voltage models we found that the Voc, for a given short-circuit current, also exhibits a poorer TDD tolerance for GaAs n+∕p solar cells compared with GaAs p+∕n solar cells. Experimentally, the open-circuit voltage (Voc) for the n+∕p GaAs solar cell grown on a SiGe substrate with a TDD of ∼1×106cm−2 was ∼880mV which was significantly lower than the ∼980mV measured for a p+∕n GaAs solar cell grown on SiGe at the same TDD and was consistent with the solar cell modeling results reported in this paper. We conclude that p+∕n polarity GaAs junctions demonstrate superior dislocation tolerance than n+∕p configured GaAs junctions, which is important for optimization of lattice-mismatched III–V devices.

The growth and properties of wide bandgap (AlxGa1-x)0.51In0.49P layers and solar cells grown by solid source molecular beam epitaxy were examined to correlate the impact of growth conditions and in-situ annealing on photovoltaic performance. A P-2:III flux ratio of 12 was found to optimize the optical qualities of Ga(0.51)ln(0.49)P epilayers. Ga0.51In0.49P solar cells were grown and subjected to different in-situ annealing conditions. The effect of annealing on material quality and. device performance was characterized through deep level transient spectroscopy (DLTS) and photoluminescence (PL), which revealed a trend in non-radiative recombination. The results suggest that removal of a deep level near Ec - 0.78 eV in the n-type base is responsible for the observed improvement in current collection seen after anneal. After refinement of the Ga0.51In0.49P growth, wider bandgap material was investigated for future use in a high temperature/high intensity solar cell. A range of (AI(x)Ga(1-x))(0.5)In0.49P materials, with direct bandgaps from 2.09 eV to 2.26 eV have been successfully demonstrated using digital alloying and conventional bulk growth.

The minority carrier lifetime of electrons (τn) in p-type GaAs double heterostructures grown on GaAs substrates and compositionally graded Ge/Si1−xGex/Si (SiGe) substrates with varying threading dislocation densities (TDDs) were measured at room temperature using time-resolved photoluminescence. The electron lifetimes for homoepitaxial GaAs and GaAs grown on SiGe (TDD∼1×106 cm−2) with a dopant concentration of 2×1017 cm−3 were ∼21 and ∼1.5 ns, respectively. The electron lifetime measured on SiGe was substantially lower than the previously measured minority carrier hole lifetime (τp) of ∼10 ns, for n-type GaAs grown on SiGe substrates with a similar residual TDD and dopant concentration. The reduced lifetime for electrons is a consequence of their higher mobility, which yields an increased sensitivity to the presence of dislocations in GaAs grown on metamorphic buffers. The disparity in dislocation sensitivity for electron and hole recombination has significant implications for metamorphic III-V devices.

GaAs solar cells grown on SiGe/Si virtual substrates in the n/p configuration are of interest to develop III-V/Si cell technologies with high radiation-tolerance and to demonstrate the general applicability of SiGe/Si substrates for transfer of standard multi-junction configurations. This paper reports the first study of minority carrier electron lifetimes in p-type GaAs base materials grown on low dislocation density (1/spl times/10/sup 6/ cm/sup -2/) SiGe/Si substrates and the first study of n/p III-V cells grown on SiGe as a function of threading dislocation density. Minority carrier diffusion lengths of /spl sim/4 /spl mu/m, well in excess of a typical n/p cell base thickness, are demonstrated and correlations between diffusion length and dislocation density are made. Preliminary cell results match theoretical predictions, and n/p GaAs cell efficiencies on Si in excess of 15% have been achieved. In parallel developments for p/n cells, GaAs cell areas on SiGe have been increased from 0.36 cm/sup 2/ to 4 cm/sup 2/ with no decrease in cell performance. This indicates that thermal stress induced microcracks are not limiting cell performance on SiGe/Si substrates at this stage of development. The cumulative impact of these results indicate the growing promise of SiGe virtual substrates for achieving high performance III-V solar cells grown on Si substrates utilizing SiGe buffer layers.

The growth and structural properties of low-temperature GaAs (LT-GaAs) films grown on Ge/SiGe/Si substrates using solid-source molecular-beam epitaxy were investigated. Identical structures were also grown on both Ge and GaAs substrates in order to ascertain the effects of heterovalent interfaces, lattice mismatch, and surface morphology on the structural properties and excess As incorporation of LT-GaAs. Triple-axis x-ray diffraction measurements revealed nearly identical lattice expansion due to excess As incorporation for LT-GaAs layers on all substrates, with the excess As concentration estimated to be 0.34%. Subsequent in situ annealing resulted in complete layer relaxation coupled with the formation of randomly distributed As precipitates of similar sizes throughout the LT-GaAs layers on each substrate as determined by transmission electron microscopy. Secondary ion mass spectroscopy measurements confirmed the incorporation of excess As to be identical for growth on each substrate type, indicating that LT-GaAs with ideal structural properties can be grown on compositionally graded SiGe/Si substrates with no apparent impact from crosshatched surface morphology or heterovalent interfaces.

Progress in creating thin film relaxed lattice constant semiconductors on conventional substrates has recently led to progress in a variety of electronic and optoelectronic devices. By understanding the relationship between misfit and threading dislocations, and the relationship between dislocation nucleation and threading dislocation propagation, graded composition buffer layers can be used to relieve lattice mismatch and retain surface layers with great perfection. A particularly interesting system is the relaxed Si/sub 1-x/Ge/sub x//Si system, which can host a variety of high performance CMOS devices as well as allow for the integration of GaAs with Si. Optical links, solar cells, and more recently, continuous wave room temperature lasers have been created on GaAs/Ge/SiGe/Si. Commercialization of relaxed Si/sub 1-x/Ge/sub x//Si materials will likely occur through the Si CMOS end market, creating a supply of low cost SiGe virtual substrates for other application areas, including solar cells.

The use of compositionally graded SiGe buffers to bridge material mismatches between GaAs based III-V compounds and Si substrates has shown extreme promise as the means by which high efficiency III-V solar cells can be integrated with low-cost Si substrates. In this paper, we describe recent progress in three areas that are critical to realize the potential of GaAs/Ge/SiGe/Si integration for photovoltaic technologies of the future. First, we show that pn configured GaAs cells are much less sensitive to dislocation-related degradation than np configured cells, indicating a preferred polarity for heteroepitaxial III-V solar cells. Second, by correlating direct, microscopic observation using cross sectional TEM and EBIC with subGaAs bandgap light I-V studies, we show that interface states present at the GaAs/Ge interface unrelated to antiphase domains are responsible for uncontrolled sub-GaAs bandgap PV response for pn cells. Further, we demonstrate a solution to this problem that completely eliminates and reproducibly controls such interfacial activity. Finally, GaAs/Ge/SiGe/Si cell areas are increased from 0.36 cm to 4 cm without reduction of cell performance, the first experimental evidence that no fundamental limitations are evident for scaling III-V/Ge/SiGe/Si cells to large areas.

In/sub 0.53/Ga/sub 0.47/As-based monolithic interconnected modules (MIMs) of thermophotovoltaic (TPV) devices lattice-matched to InP were grown by solid source molecular beam epitaxy. The MIM device consisted of ten individual In/sub 0.53/Ga/sub 0.47/As TPV cells connected in series on an InP substrate. An open-circuit voltage (V/sub oc/) of 4.82 V, short-circuit current density (J/sub sc/) of 1.03 A/cm/sup 2/ and fill factor of /spl sim/73% were achieved for a ten-junction MIM with a bandgap of 0.74 eV under high intensity white light illumination. Device performance uniformity was better than 1.5% across a full 2-in InP wafer. The V/sub oc/ and J/sub sc/ values are the highest yet reported for 0.74-eV band gap n-p-n MIM devices.

Si-doped InAs x P 1-x layers with As mole fractions ranging from 0.05 to 0.50 were grown on InAs x P 1-x step-graded buffer layers on InP substrates by solid source molecular beam epitaxy. The growth parameters consisted of a P:In flux ratio of 7:1, a growth temperature of ~ 485°C, a growth rate of 2.2 Å/s, and an As:In flux ratio of 0.37-2.36 for varying As mole fractions. The As mole fraction and the layer relaxation were determined using triple axis x-ray diffraction measurements. Near complete relaxation (>93%) was achieved for all Si-doped InAs x P 1-x epilayers. The structural morphology indicated that the InAs x P 1-x graded buffer layers were effective in relieving the lattice mismatch strain as evidenced by a well-developed crosshatch morphology and low rms surface roughness. The electron concentration, mobility, and Si donor activation energy for each InAs x P 1-x composition were determined using temperature dependent Hall measurements. At a constant electron carrier concentration of %3.5×10 16 cm -3 , the 300 K carrier mobility increased from 2700 to 4732 cm 2 /V-sec with increasing As mole fraction from 0.05 to 0.50.

Single junction InGaP/GaAs solar cells displaying high efficiency and record high open-circuit voltage values have been grown by metal-organic chemical vapor deposition on Ge/graded SiGe/Si substrates. Open-circuit voltages of 980 in 17 under AM0 conditions have been verified to result from a single GaAs junction, with no evidence of Ge-related sub-cell photoresponse. AM0 efficiencies close to 16% have been measured for a large number of small-area cells, the performance of which is limited by non-fundamental current losses due to significant surface reflection resulting from >10% front-surface metal coverage and wafer handling during the growth sequence for these prototype cells. It is shown that at the material quality currently achieved for GaAs grown on Ge/SiGe/Si substrates, namely a 10 ns minority-carrier lifetime that results from complete elimination of anti-phase domains, and maintaining a threading dislocation density of -8 x 10(5) cm(-2), 19-20% AM0 single-junction GaAs cells are imminent. Experiments show that the high performance is not degraded for larger-area cells, with identical open-circuit voltages and higher short-circuit current (due to reduced front metal coverage) values being demonstrated, indicating that large-area scaling is possible in the near term. Comparison with a simple model indicates that the voltage output of these GaAs-on-Si cells follows the ideal behavior expected for lattice-mismatched devices, demonstrating that unaccounted-for defects and issues that have plagued other methods to epitaxially integrate III-V cells with Si are resolved by using SiGe buffers and proper GaAs nucleation methods. These early results already show the enormous and realistic potential of the virtual SiGe substrate approach for generating high-efficiency, lightweight and strong 111-V solar cells. Copyright (C) 2002 John Wiley Sons, Ltd.