Due to the rising complexity of modern chip designs, the connection of the different on-chip IP cores has become an important issue. To establish communication links between computation nodes either wide busses or fast serial data paths - so called networks on chip (NoC) - are necessary, depending on the application and the chip design. In case of the serial links a variety of different algorithms and topologies are cogitable, which have to be evaluated and tested to find the optimal solution for a given problem. To do this, the NoC can be emulated on a hardware platform based on FPGAs to exploit the flexibility for short turn-around-times and achieve nearly real time conditions by accelerating the test process. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient network on chip (NoC) implementation based on Xilinx Virtex-II FPGAs

RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of rapid prototyping (RP) another feature plays an important rule: their infinite re-programmability. These features help to create freely modifiable Rapid Prototyping systems, which allow both, changes in the hardware architecture as well as in soft-ware. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA- based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration.

In the last years FPGAs have become very important for electronic designs - they are very flexible, provide high configurability and allow short turn around times. Especially for rapid prototyping (RP) another feature plays an important rule: the nearly infinite reprogrammability. However, handling these devices in the engineering process is not an easy issue. Therefore our approach presents an efficient, flexible and versatile FPGA configuration methodology based on partial bitstream merging at design time

The novel platform concept and system design methodology the development process is shortened, which accelerates the complete design process and allows quick turn around times. For this, no knowledge of FPGA design or hardware description languages as VHDL or Verilog is necessary

RAM-based FPGAs have become very important for electronic designs in the last years since they are very flexible, provide high configurability and allow short turn around times. Especially in the field of rapid prototyping (RP) another feature plays an important rule: their infinite reprogrammability. These features help to create freely modifiable rapid prototyping systems, which allow both, changes in the hardware architecture as well as in software. However, handling the FPGA devices in the engineering process is not an easy issue and typically requires deep knowledge of the circuits themselves, their behavior and programming languages as VHDL or Verilog. Our approach presents the combination of a flexible and versatile FPGA-based rapid prototyping system and efficient configuration methodology for Xilinx Virtex-II FPGAs supplemented by an easy to use design support for time saving functional implementation and platform configuration

Duetotherising complexity ofmodernchipdesigns, theconnection ofthedifferent on-chip IPcoreshasbecomean important issue. Toestablish communication links between com- putation nodeseither widebusses orfastserial datapaths - so called networks onchip(NoC)-arenecessary, depending onthe application andthechipdesign. Incaseoftheserial links avari- etyofdifferent algorithms andtopologies arecogitable, which havetobeevaluated andtested tofind theoptimal solution fora given problem. Todothis, theNoCcanbeemulated onahard- wareplatform basedonFPGAstoexploit theflexibility forshort turn-around-times andachieve nearly realtimeconditions by accelerating thetest process. Ourapproach presents thecombina- tionofa flexible andversatile FPGA-based rapidprototyping system andefficient network onchip(NoC)implementation based onXilinx Virtex-It FPGAs.

In this paper we present a new concept of a configurable modular rapid prototyping system called COMPASS (configurable modular platform for automotive systems). Our ambition is to support the design engineer in all phases of the rapid prototyping (RP) process, including the concept-oriented, the architecture-oriented and the realization-oriented RP. Therefore we provide one unique and flexible development platform that covers all phases. The overall performance and flexibility is reached by the special system structure and the intensive use of FPGAs in combination with a high performance processor. This offers the potential to implement automotive applications with highly specialized peripherals, fast interfaces and communication channels to cope with today's requirements. Moreover programmable logic devices allow hardware reuse to a very high degree in contrast to existing commercial products. The proposed platform saves costs since the versatile configurable interface cards can be used for different purposes and so feature benefits over function specific hardware modules. As a special bonus the flexible and adaptive structure of the platform associated with the reconfigurability of the modules is not only restricted to RP, but also permits the usage as a hardware-in-the-loop (HiL) test system.

This paper focuses on the combination of educating hardware as well as software development in one laboratory. The needs to offer such a co-training concept arise from the demands of industry towards the desired skills of today's engineers. Their view must no longer be restricted to his/her own work, but has to be widened to a complete system view. To provide an appropriate educational scheme, the university courses have to adapt to these changes. Therefore an innovative lab concept is presented here. The goal is to improve student's skills in multiple directions to deliver an efficient inter-disciplinary hardware/software lab course, based on the training of state-of-the-art industrial architectures and relevant tools.

This paper describes the combination of educating both, hardware and software with one practical lab. The needs to offer such a co-training concept are brought out by the demands of industry towards the desired skills of today's engineers. An engineer's view must no longer be restricted to his/her own work, but has to be widened to a complete system view. To provide an appropriate education scheme the university courses have to adapt to these changes. Therefore an innovative lab concept is presented here. Its goal is to improve students skills not only in a single direction, but to deliver an efficient inter disciplinary hardware software lab course, combined with training state-of-the-art industrial architectures and relevant tools.