MLIR (Multi-Level Intermediate Representation) has proven to be a scalable framework for building modern compilers. A key challenge, however, lies in effectively provide these compilers with input programs. Several methods have been explored: static methods, such as Domain-Specific Language, generic language front-end that transform an abstract syntax tree using tools like Polygeist, or leveraging compiler intermediate representation with Brutus. Dynamic approaches, such as tracing with JAX or Reactant, offer another solution. Each class of methods presents trade-offs: static approaches are easily integrated through compiler passes but lack runtime information, while dynamic tracing captures runtime behavior but cannot handle compile-time information. In this paper, we propose enhancing the Reactant tracing system by integrating the Julia compiler static analysis. This hybrid approach improves the expressiveness and precision of tracing. The effectiveness of our approach is demonstrated on the Polybench benchmark suite.
Open-source descriptions of RISC-V processors have been around for a while. Making hardware designs freely available is a key part of open silicon initiatives. An open-source implementation allows peers to easily reproduce each other's findings and to improve on previous results. The challenge lies in the integration of third-party technologies into new projects. The best known open-source RISCV platforms are described in SystemVerilog. This language allows for the description of hardware and the automatic verification of complex systems. However, as more components are aggregated into a project, it becomes challenging to keep up with development times. Hardware "blocks" can alleviate this problem. By packaging HDL components as individual modules and connecting them through a graphic interface, it is possible to deploy large architectures in a matter of minutes. In our work, we discuss the adoption of this design methodology in the design flow of RISC-V-based SoCs. We show that by wrapping RISC-V cores as individual modules, it is much easier to prototype these platforms. As proof of concept, we introduce RISC-B, a freely available repository for RISC-V blocks compatible with the AMD-Xilinx design flow.
Iterative stencil loops are a widely used class of matrix algorithms, with applications in the fields of image processing, neural networks, scientific computing, and mathematics. They are, however, very vulnerable to memory bottlenecks from reading large amounts of repeated data. This paper aims to study the cache usage of stencils, and proposes an implementation of the data-locality management unit (DMU) as a tool accelerate stencil execution. The DMU is a programmable memory controller for managing main memory reads and data reorganisation. Finally, this paper uses simulated behavioral models of the architecture to examine the effect of the DMU on both memory reads and CPU load. Initial tests showed a reduction of 50% in both CPU instructions and DRAM loads when using the DMU, when compared to unoptimised stencil code, and a similar reduction in memory reads even compared to highly optimised stencil code.
Autonomous driving research is progressing rapidly, but practical deployment demands strict real-time, safety, and security guarantees. While AUTOSAR Adaptive Platform (AUTOSAR AP) and Robot Operating System 2 (ROS 2) each meet these requirements and can be collaborated, end-to-end latency analysis in a mixed environment remains challenging. This paper proposes CART (Combined AUTOSAR AP and ROS 2 Tracing), which converts AUTOSAR AP trace data into a ROS 2-compatible format for unified analysis. We then demonstrate how CART enables seamless end-to-end latency measurement across both platforms, pinpoints bottlenecks, and accelerates iterative design-and-test cycles to support rapid prototyping of autonomous driving systems.
Programs executed on a Java Virtual Machine ( JVM) such as Eclipse OpenJ9 are initially interpreted. To enhance performance, Justin-Time ( JIT) compilers are used to compile frequently executed code paths into native machine code. Although the default optimizing compiler in OpenJ9, Testarossa (TRJIT), produces highly tuned native code, its compilation overhead may not be ideal for memory-constrained or latency-sensitive environments. Currently in development, MicroJIT is a lightweight, template-based compiler in OpenJ9 that generates fast, non-optimized native code with minimal overhead, working in tandem with TRJIT. However, the MicroJIT compilation pipeline suffers from wasted work when it encounters any currently unsupported bytecodes during the code generation phase, resulting in unnecessary partial compilations and performance regressions. This work introduces a pre-compilation validation phase with a new method that detects cases of unsupported bytecodes within a method before any object construction or machine code generation begins. This implementation reduces unnecessary utilization of resources by preemptively detecting and aborting invalid compilations. The implementation was evaluated using the DaCapo benchmark suite and other custom methods under controlled runtime conditions. Our results show that this improvement preserves correctness while reducing redundant compilation attempts, therefore improving efficiency.
Software development often relies on cycle-accurate simulations to accurately estimate application execution time. While these simulations provide detailed results, they can be time-consuming and impractical for complex applications. In the early stages of design, when multiple iterations are required, high simulation speed is key to optimizing the process. To achieve this, abstract performance models are often manually derived from hardware specifications or lower-level implementations (e.g. RTL). We propose to automate the generation of performance models from accurate low-level simulations using ML techniques. The generated models are then composed with fast simulators, providing an efficient and accurate framework for functional and performance evaluation on target hardware architectures. Applied to the CVA6 RISC-V architecture and the QEMU emulator, our method achieved an average prediction error of less than 7%, with minimal speed overhead compared to QEMU, and up to 29400x speedup with respect to Verilator.
With the increasing core counts in chip multiprocessors (CMPs), traditional electrical networks-on-chip (eNoCs) are facing limitations in energy efficiency, bandwidth, and scalability. Optical integrated networks (OINs) have emerged as a promising alternative, offering high bandwidth, low energy consumption, and native support for broadcast communication. However, the effectiveness of OINs is often constrained by the latency and complexity of their control planes, especially in large-scale systems. This paper introduces CLAP, a fully decentralized, asynchronous control mechanism designed to overcome these challenges. CLAP leverages a modular, clockless architecture based on click elements to enable low-latency, scalable routing without the need for global synchronization. Simulation and synthesis results confirm CLAP's high performance and low overhead, demonstrating its suitability for high-performance OINs across a range of network sizes.
Continuous blood pressure (BP) monitoring is essential for managing hypertension and preventing cardiovascular events. However, current state-of-the-art machine learning models rely on computationally expensive architectures such as Transformers and ResNets, often require handcrafted features or additional sensors like ECG, and are unsuitable for wearable and battery-constrained devices. In this work, we propose a lightweight, end-to-end regression model that estimates systolic and diastolic BP directly from raw photoplethysmogram (PPG) signals. The model leverages a compact U-Net architecture integrated with Channel Prior Convolutional Attention (CPCA) modules to efficiently extract multiscale temporal features with minimal computational overhead. Our method achieves competitive performance, with a mean absolute error (MAE) of 4.48 mmHg for systolic blood pressure(SBP) and 2.9 mmHg for diastolic blood pressure (DBP), while significantly reducing the number of parameters, floating-point operations (FLOPs), and energy per inference operation compared to conventional deep models. This makes it highly suitable for always-on, wearable BP monitoring. This project lays the foundation for a hybrid framework combining early-stage classification with detailed blood pressure estimation, to be developed in future work.
Traffic managers in programmable networks remain rigid and underexplored due to the lack of prototyping tools that support rapid design iteration and runtime reconfigurability. This paper presents a novel architecture and prototyping methodology for a programmable scheduler, built around lightweight nodes interconnected via a Network-on-Chip (NoC). Each node embeds a 32-bit RISC-V processor and configurable scheduling logic, allowing dynamic realtime policy updates through hot-swappable instruction memory. Our approach spans multiple abstraction levels: at the behavioral level, we extend BMv2 with a P4 interface to prototype and test scheduling policies within programmable data planes, while a SystemC model deployed with High-Level Synthesis (HLS) supports hardware refinement and FPGA deployment. The architecture enables modular, scalable, and reconfigurable traffic management by decoupling scheduling logic from fixed RTL and centralized memory. This work lays the foundation for rapidly prototyping diverse scheduling policies and exploring hardware/software co-design for adaptive data plane systems.
Because systems' complexity keeps increasing at a fast rate, designers rely on a combination of languages and tools to ease the design process and reduce development time. However, there are many options to choose from, and it is up to the designer to find the most fitting combination of languages, tools and solutions to apply. For this reason, this paper presents the methodology followed to successfully implement a RISC-V based control system for 3-phase Permanent Magnet Synchronous Motors (PMSM), the languages and tools used, as well as the design choices made and the overall impact on the system's performance.
Modern edge computing systems must balance performance and energy efficiency under constrained power budgets. We present ADAM (ADAptive Microcontroller), an open-source and parametric RISC-V platform designed to explore architectural and softwarelevel mechanisms for energy-aware embedded computing. ADAM supports heterogeneous cores organized into separate low-power and high-performance domains, enabling partitioned execution across a range of workload intensities. The platform introduces the Activity Pause Protocol, a software-driven interface for coordinating clock and power gating transitions, and includes a hybrid evaluation flow that combines FPGA execution with post-synthesis RTL simulation using execution context snapshotting. We demonstrate ADAM's capabilities with a keyword spotting use case, highlighting how domain separation and programmable power management reduce energy consumption by up to 38% in intermittent workloads.
FPGA-accelerated simulation offers a promising path toward achieving fast and cycle-accurate architectural evaluations. However, while platforms like FireSim significantly improve simulation speed compared to traditional software-based simulators, they still pose usability challenges for rapid microarchitectural prototyping due to the complexity of register-transfer level (RTL) development. In this work, we present a modular and latency-insensitive interface that simplifies the integration of cache replacement policies into FireSim's L2 cache. Our approach supports multiple implementation strategies, including host-based software, RTL, and high-level synthesis (HLS), thereby enabling multiple tradeoffs between simulation speed, hardware resource usage, and development effort. We use the advanced Hawkeye replacement policy as a case study to demonstrate the versatility of our approach and evaluate tradeoffs among the different implementation strategies. Our results show that, with the proposed latency-insensitive L2 interface, the HLS strategy strikes a favorable balance: It incurs only a 1.57x simulation slowdown compared to baseline FireSim, while avoiding the need for RTL expertise and significantly reducing design effort. Latency-insensitive interfaces therefore make it practical and efficient for non-hardware experts to evaluate advanced cache replacement policies on FPGA-accelerated simulators.
In the domain of formal verification, translating natural language (NL) requirements into Computation Tree Logic (CTL) specifications presents a notable challenge due to the disparity between human-readable documents and formal specifications. This paper introduces a novel approach that leverages Large Language Models (LLMs) to automate this translation process, thereby enhancing the accuracy and efficiency of formal verification practices. We fine-tune three state-of-the-art LLMs—LLAMA3, Mistral, and Qwen2—with a particular focus on optimizing the Mistral model due to its superior performance. Our methodology is supported by the Natural2CTL dataset, consisting of 2,095 NL requirements and their corresponding CTL specifications. We employ evaluation metrics such as validation loss, accuracy, semantic similarity, and Structural Operator Jaccard Similarity (SOJS) for a comprehensive assessment of model performance. Additionally, a comparative analysis with human translators, trained in CTL logic, underscores the LLMs’ potential to match or even surpass human accuracy in translating NL requirements into formal specifications. Our findings reveal that the fine-tuned Mistral model significantly outperforms the other LLMs and human participants, demonstrating superior accuracy in generating CTL specifications. This study advances the field of formal verification by proposing a scalable solution to the NL-to-CTL translation challenge, setting a new benchmark for the integration of AI tools in complex specification tasks.
The diversity of Instruction Set Architectures (ISAs), each with its unique constraints and optimization strategies, presents significant opportunities and challenges in processor design. Modern processor vendors exploit these ISAs to enhance security, reliability, and performance. Recent security vulnerabilities, notably Spectre and Meltdown, have highlighted the critical need for robust hardware security measures. In this paper, we employ gem5, a state-of-the-art cycle-accurate simulation tool, to simulate the Spectre attack. We developed and modified scripts for both x86 and ARM architectures to ensure compatibility with gem5 version 23.1. Our simulation setup involved running attack scenarios under various configurations to gather comprehensive data on cache misses, cache hits, mispredicted branches, and level 2 cache hits and misses. In the simulation, we analyzed the trace files generated by gem5, utilizing a range of debug flags such as Exec for disassembly (dasm) insights. By detailed analysis of cache and branch prediction using detailed debug data revealed by gem5 traces, we identify some specific attack patterns that are useful for automating the detection of the attacks. Our future work aims to expand this analysis to include additional attack vectors and find more attack patterns, thereby strengthening our attack pattern recognition capabilities.
This study optimizes the Verilog-to-Routing (VTR) flow, an open-source Computer-Aided Design (CAD) tool. It utilizes ODIN II and Parmys for synthesis, ABC for technology mapping, and Versatile Place and Route for packing, placement, and routing. The ABC9 optimizations, integrated as a pass within the Yosys Open Synthesis Suite, enhance technology mapping and optimization stages and outperform the traditional ABC tool for large, complex designs. These optimizations improve timing behavior in multi-clock designs and include a delay model for Field Programmable Gate Array (FPGA) hard blocks. Various benchmarks assess the effectiveness of the workflow across different design complexities and FPGA architectures, including the utilization of hard blocks.
There is a conceptual divide between the ways cryptographic algorithms are defined (i.e., informal imperative pseudocode) and commodity hardware design languages (e.g., Verilog). How does one even begin to compare a pseudocode to an HDL design that purports to implement it in hardware? Bridging this divide requires substantial manual intervention and, consequently, “shrinking the divide” can drastically reduce the cost of high-assurance cryptographic hardware by reducing the cost of formal verification. We present a correct-by-construction methodology for the functional hardware design language, ReWire, in which a reference cryptographic algorithm is transformed into a provably correct hardware design with a program transformation called temporal staging. We illustrate this methodology with case studies including one for the BLAKE2b cryptographic hash function. Because the reference algorithm, the temporal staging transformation, and the resulting implementation are all expressed in ReWire, formal verification can proceed immediately via a published ReWire semantics.
The page size used for virtual to physical address translation has globally not changed since the late 1960’s: the IBM 360, circa 1964, already had 4 KiB pages. This 4 KiB page size has proven to be incredibly robust given the changes in processor architectures, workloads behavior, memory size, and access patterns. However, with 64-bit registers, 57-bit virtual addresses, and increasingly bigger physical memories, we have to ask ourselves whether 4 KiB is still an adequate page size for modern workloads on modern machines. Inherently, the page size has an influence on (a) the miss rate of the translation lookaside buffer, the cache that contains the recently used virtual to physical translations, and (b) the memory allocated by the system versus the memory actually used by a process. The page size also constraints some microarchitectural choices, such as cache design, which impacts the overall performance and energy efficiency. We focus more particularly on High Performance Computing (HPC) applications because they are extremely demanding in terms of memory, and are indicative of future general-purpose needs.In this paper, we empirically study the evolution of the miss rate and memory occupancy with respect to the page size, and conclude that a page size of 32 KiB is better suited for current HPC systems. We also propose a page table scheme for RISC-V-based HPC systems based on our observations and discuss its benefits.
The Fiduccia-Mattheyses-Sanchis (FMS) algorithm is a widely used local search method for K-way circuit partitioning, but it’s prone to getting stuck in local minima. Traditionally, this has been addressed by running FMS multiple times with different random initial solutions, hoping for a better result. Building on our previous work with an RL-based local search method that helps FMS avoid these traps, this research explores a new approach: using constructive methods to generate superior initial solutions. We explored two such methods: NDE (node growing algorithm), a commonly used node-based method that maximizes node absorption, and NET (net growing algorithm), an edge-based approach that maximizes net absorption. By integrating NDE and NET with our RL-based local search, we’ve achieved significant improvements. Experiments on ISPD98/IBM benchmarks demonstrate that an edge-based approach provides higher-quality solutions for larger circuits and larger numbers of partitions. Combining these initial solutions with our RL-based approach further reduces the cutsize generate by the RL-based approach by up to 79.5%.
We demonstrate how dynamic verification (e.g. simulation) can be replaced by deductive formal verification and how to benefit from the advantages of symbolic verification and the reuse of verification proofs. To do this, we swap the well-known module-hierarchy based concept with a transaction-level (TL) based alternative, which still allows us to describe the design as precisely as on RTL. We enhance the aspect-oriented and TL oriented language PDVL to support the definition of functional coverage (FC) and assertions at all levels of a TL-hierarchy.We then show how to use a deductive formal verification (DFV) flow which compiles PDVL code into Gallina code to be used by the Coq theorem prover. It can be argued that FC can be converted into proof obligations and that proving them is equivalent to 100% coverage. We also demonstrate how lower-level proofs can be reused when verifying aspects at higher-levels of a TL-hierarchy. We argue that the traditional assertion-based verification (ABV) methodology is still supported and SVA can be proven using DFV.
With increasing aging problems of advanced technologies, in-field testing becomes an inevitable challenge, on top of the already demanding requirements, such as the ISO26262 for automotive safety. SOCs used in space, automotive or military applications in particular are worst affected as the in-field failures in these applications could even be life threatening. We focus on on-line and in-field testing for Single Event Upsets (SEU, caused by a single ionizing particle) and aging defects (such as delay variation and stuck-at faults) which may appear during normal operation of the device. Interrupting normal operations for aging defects testing is a major challenge for the OS. Additionally, checkpointing with rollback-recovery can be costly and mission critical data can be lost in case of an SEU event. We eliminate many of these problems with our non-interfering in-field testing and recovery solution.We apply a hardware performance improvement technique called System Hyper Pipelining (SHP), which combines well-known context switching (Barrel CPU) and C-slow retiming techniques. The SoC is enhanced with an SEU detection and ultra-fast recovery mechanism. We also use an RTL ATPG framework that enables the generation of software-based self-tests to achieve 100% coverage of all testable stuck-at-faults. The paper finishes with very promising performance-per-area and test-cycles-per-net results. We argue that our robust system architecture and EDA solution, designed and developed primarily for in-field testing of SoCs, can also be used for production and on-line testing as well as other applications.
