In this article, the impact of device architecture on threshold voltage VTH instabilities during OFF state operation under a high drain voltage stress on GaN-on-Si MOSc HEMTs is thoroughly investigated. Measurement-stress-measurement high-voltage bias temperature instability (HVBTI) technique using ultrafast VGS ramp was used in this study. This measurement technique was carried out on various gate length (L-G), ohmic length (L-OHM), and field plate (FP) length. HVBTI transients performed at different L-G highlight that increasing the gate length induces a better electrostatic control under the gate via a gate shielding. TCAD simulations support the claim that the relaxation peak is linked to the charge redistribution of ionized C-N (-) traps under the gate. This charge redistribution during the relaxation phase is enhanced using a larger ohmic contact area. The electric field at gate and source FP corners has a strong impact on ionized C-N acceptor traps located in the GaN:C layer close to the gate and consequently on positive VTH degradation observed for short stress duration. Substrate biasing and TCAD simulations suggest that the C-N traps' deionization and trapping in the volume of the gate oxide is related to the presence of free holes in the GaN:C layer.

In this paper, we review the gate reliability of the GaN MOSc-HEMT as well as the specific method to address the peculiarities of these transistors. The long term forward gate TDDB will be explored showing the impact of the gate recession and gate material on the expected maximum gate oxide field $(\mathbf{E_{OX, MAX}})$ at 10 years. The gate related threshold voltage instabilities (pBTI and nBTI) are reviewed showing the interplay between epitaxy material and gate oxide process. Finally, the high drain voltage influence on Vth (HVBTI) is studied through the development of specific and dedicated setup allowing a deeper understanding of the device instabilities during operation.

In this paper, we present a general overview of AIGaN/GaN MOS channel High Electron Mobility Transistor (HEMTs) with fully recessed gate architecture fabricated on 200mm Si-wafer. Specifically, an insight on its benefits compared to market competitors is brought out respectively from transistor electrical characteristics to robustness behavioral aspects.

In this paper, we review the nature of traps population and the transport mechanisms in GaN-on-Si E-mode MOS channel HEMTs during High Voltage Bias Temperature Instabilities (HV-BTI) test under various temperatures (T), drain voltage stress (VDSstress) and gate voltage stress (VGSstress) conditions. Thanks to experimental setup using ultra-fast I D (VG) to monitor VTH during both stress and recovery phases from 10µs to several kiloseconds. The temperature dependent measurements show that V TH and RON degradations are related to the CN deep acceptor traps in GaN:C layer. Two mechanisms during the stress phase are identified, CN traps deionization first, impacted by VDsstress, then nBTI behavior influenced by VGSstress. It is observed that high drain voltage stress (≥ 200V) induces a charge redistribution predominantly towards the drain node, while a lower drain voltage stress led to a charge redistribution in the source-gate region.

In this paper, we propose a novel characterization methodology to study dynamic RON and VTH during a high voltage stress on the drain node of GaN-on-Si E-mode MOSc-HEMTs using a half-bridge configuration circuit and specific gate voltage waveforms. This novel setup enables to study simultaneously RON and VTH during stress and recovery phases from 10µs to several kiloseconds. At 150°C a high carbon concentration in Carbon-doped GaN layer, reduces ON-Resistance degradation. Temperature dependent measurements show that RON degradation is related to CN acceptor traps in the GaN:C layer. High voltage drain stress induces a combination of VTH drift and access region related dynamic RON effect.