In this paper, we review the nature of traps population and the transport mechanisms in GaN-on-Si E-mode MOS channel HEMTs during High Voltage Bias Temperature Instabilities (HV-BTI) test under various temperatures (T), drain voltage stress (VDSstress) and gate voltage stress (VGSstress) conditions. Thanks to experimental setup using ultra-fast I D (VG) to monitor VTH during both stress and recovery phases from 10µs to several kiloseconds. The temperature dependent measurements show that V TH and RON degradations are related to the CN deep acceptor traps in GaN:C layer. Two mechanisms during the stress phase are identified, CN traps deionization first, impacted by VDsstress, then nBTI behavior influenced by VGSstress. It is observed that high drain voltage stress (≥ 200V) induces a charge redistribution predominantly towards the drain node, while a lower drain voltage stress led to a charge redistribution in the source-gate region.

To understand the peculiar kinetic of the negative Bias Temperature Instabilities (nBTI) in GaN-on-Si MOS-channel HEMTs (MOSc-HEMTs), temperature (T), gate bias (V G,stress ) and modification of the epitaxial structure are used to determine if free holes are responsible for long-term threshold voltage (Vth) shift. Furthermore, UV assisted nBTI measurements were carried out to stimulate free holes generation in the epitaxy structure near the gate. TCAD simulations validate the assumption that nBTI is a multifactorial degradation mixing free holes capture in the Al 2 O 3 gate oxide and C N deep acceptor charge state modification in the buried GaN:C layer.

In this paper we present a detailed performance status of AlGaN/GaN MOS channel High Electron Mobility Transistors (MOSc HEMTs) with fully recessed gate architecture on 200mm Si substrates. We report a wide range of wafer and package level results. ON state resistance is studied through three aspects: i) RON partitioning with analysis of its four components, ii) RON temperature dependence, iii) cumulative dynamic RON under stress. For accurate power assessment we characterize packaged devices and compare the typical figures of merit (gate charge, switching tests) to state of the art references (especially pGaN gate HEMTs). We highlight the benefits offered by this technology for 650V applications, such as very low I GSS leakage even at 150°C, and better switching performances, t d(on) , t d(off) .

The fully recessed gate GaN-on-Si MOS-channel HEMTs (MOSc-HEMT) with Back-Barrier (BB) structure gives rise to unexpected threshold voltage (V-TH) behaviors such as V-TH increase with decreasing gate length (L-G) (V-TH roll-up) and discrepancies between V-TH values extracted from I-D(V-G) (V-TH_(IV)) and from C-GC(V-G) (V-TH_CV) characteristics. Using TCAD simulations and experimental measurements, we demonstrate that conduction band confinement, especially at gate corners, is responsible for these peculiar V(TH)( )behaviors. This band confinement is strengthened by the fully recessed gate configuration coupled with the proximity of a back-barrier.

Accurate split-CV mobility measurements require to overcome Bias Temperature Instabilities (BTI) which are a key issue in GaN-on-Si MOS-channel HEMTs (MOSc-HEMT). In this article, a rigorous methodology to extract the split-CV mobility as a function of the electron density and the temperature at Al2O3/GaN MOS interface is depicted. Drain current In(VG) and gate-to-channel capacitance CGc(VG) measurements are performed simultaneously under fast gate voltage VG ramp to prevent BTI. The voltage ramp enables fast CGC(VG) measurements and allows to bypass the frequency effect which can be observed when using small signal CGC(VG) measurements. Thus, this technique paves the way to a reliable determination of intrinsic electron transport properties of GaN transistors.

In this study, we investigate the difference between ID(VG) and C(VG) pBTI shifts on GaN-on-Si E-mode MOS-channel HEMTs, under various gate voltage stresses (VGStress) and temperatures (T). A new experimental setup using ultra-fast and simultaneous ID(VG) and C(VG) measurements enables to monitor the threshold voltage VTHdrift through two metrics, $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$. Experimental pBTI results depict a difference between $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$, such as $\mathrm{\Delta}\mathrm{V}_{\text{THI}} < \mathrm{\Delta}\mathrm{V}_{\text{THC}}$. TCAD simulations support that ID(VG) shift ($\mathrm{\Delta}\mathrm{V}_{\text{THI}}$) is related to charge trapping in Al2O3gate oxide defects at the gate corners regions while C(VG) shift ($\mathrm{\Delta}\mathrm{V}_{\text{THC}}$) is mainly ascribed to the gate bottom, due to the presence of a back-barrier layer in the epitaxy. These previous results enable to deduce that the Al2O3defects density is more important at the gate corners than at the gate bottom.

In this article, threshold-voltage V TH instabilities under positive gate voltage stress V GStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast V G ramp was applied in this study. PBTI transients performed at different V GStress and several temperatures highlight the influence of two trap populations, one being related to Al 2 O 3 gate oxide defects and the other one to C N acceptors in GaN lattice. Both trap populations are located close to the Al 2 O 3 /GaN interface and lead to V TH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8-0.9 eV related to C N traps and an energy range between 0.7 and 1.5 eV ascribed to Al 2 O 3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al2O3/UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.

In this paper, threshold voltage VTH instabilities under positive gate voltage stress (VGStress) are thoroughly investigated on GaN-on-Si Enhancement-mode MOS-channel HEMTs. An analysis of pBTI transients performed at several VGStress and temperatures (T) reveals two trap populations close to the Al2O3/GaN interface namely (1) CN acceptors in the GaN substrate, and (2) defects in the Al2O3 gate oxide. Both trap populations lead to VTH instabilities via different underlying mechanisms as evidenced by TCAD simulations. At VGStress < 1.5 V, VTH drifts are ascribed to CN traps ionization localized at 0.8-0.9eV above the valence band (Ev). At higher VGstress, electron trapping also occurs in Al2O3 defects leading to stronger VTH degradation. DC & AC pBTI transients have been modeled using Capture Emission Time (CET) map approach, which allowed the identification of both trap populations. Temperature-dependent CET maps extraction reveals a strong activation of CN traps with temperature, and confirms Arrhenius analysis consistency. This study provides a deep understanding of BTI reliability in GaN-HEMT technologies.

In this paper, we investigate the influence of negative gate stress on threshold voltage V TH instabilities in GaN-on-Si devices. This study has been carried out by using ultra-fast Measurement-Stress-Measurement (MSM) procedure on GaN-on-Si E-mode MOSc-HEMTs (Enhancement-mode MOS-channel HEMTs) for different gate lengths L G . NBTI transients at different temperatures and complementary ToF-SIMS analysis reveal the influence of two trap populations involved on V TH instabilities, both of them are related to the C N acceptor traps. The first one is close to the interface between GaN and Al 2 O 3 gate oxide due to N-vacancies induced by the dry etching process, the second one is likely to be related to GaN:C layer. NBTI transients also exhibit a dependence with L G , which is consistent with the E-field distribution of the gate region obtained by TCAD simulations at different gate stress voltages, and confirm the proximity of a C N trap population to the gate oxide.

In this paper, we explore the influence of the fully recessed gate length on threshold voltage instabilities. The study has been performed by the use of ultra-fast pBTI measurements on GaN-on-Si E-mode MOSc-HEMTs, as well as TCAD simulations. It reveals that gate length reduction tends to decrease the pBTI degradation. Transient analyses (degradation/relexation) reveal same dynamics whatever the gate length while the value of the initial V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> directly influences BTI. TCAD simulations highlight that the full recess gate configuration creates a short-channel effect responsible for this peculiar Vth degradation.