The dynamic voltage imbalance between series connected SiC MOSFETs will cause imbalanced losses and reduce voltage capacity. The existing voltage-balancing methods introduce additional losses and make the circuit design more complex and difficult to implement. This article proposes a dynamic voltage-balancing method using external drain-gate compensation capacitors, which leads to almost no additional losses, maintains a simple circuit structure, and is easy to implement. An analytical voltage-sharing model is established. The impact paths and degrees of different parasitic parameters on the imbalanced voltage are obtained. The key parameters that induce the imbalance voltages have been identified. Based on the model's conclusions, this article presents a voltage-balancing method using external drain-gate compensation capacitors. Then, a power module with three MOSFETs in series is designed, fabricated, and optimized. Finally, a 1500 V/45 A double-pulse test platform is established to validate the effectiveness of the proposed method. The experimental results showed that the imbalance voltages of MOSFETs were reduced by more than 90% after the optimization. Additionally, pulse experiments conducted under various operating conditions further demonstrated the effectiveness of the proposed method.

Press-pack IGBTs (PP-IGBTs) are widely used due to their high power, double-sided cooling, and easy series connection. However, the external pressure on the large-area boss is uneven due to the non-uniform strain caused by the mismatched thermal expansion coefficients (CTE) between different materials. This can lead to problems such as edge warping, temperature concentration, and chip cracking during operation. This paper proposes a method to replace the traditional pure molybdenum plates with a gradient copper-molybdenum alloy ratio layout. The results show that increasing the copper proportion in the central region appropriately can reduce the maximum junction temperature by 1 °C, improve the temperature and pressure uniformity of the module chip by up to 7.47% and 14.12% respectively, along a single path, and by 7% and 2% across the entire module. However, a large gradient can impair the stress transfer mechanism, leading to an excessive level of internal stress. This simple and effective method is applicable for high-power applications of PP IGBTs and scenarios with good heat dissipation conditions.

The double-side cooling (DSC) power modules are sandwich packaged with DBC substrate, spacer, and connection column. The interconnection structure, including the circuit layout on DBC, chips layout, and connection column layout, all has influence on the thermo-mechanical behavior of the DSC packaging. This paper built a model based on the interconnection structure of the commercial DSC half-bridge power module and analyzed its thermal stress performance. It is found that the chip layout is in position where the substrate deformation is large, which causes thermal stress concentration in the solder layers. To reduce the thermal stress concentration caused by the structure and layout, a new H-type interconnection structure is proposed in this paper. By setting multiple connection columns and adjust circuit layout, the thermal deformation of the upper and lower substrates is suppressed, which can reduce the thermal stress of the solder layer and improve the reliability of the package. The simulation and experimental results show that the proposed structure has lower thermal stress performance and longer power cycling life, which verifies the effectiveness of the designed structure.

Understanding the sintering behavior and mechanical failure mechanism of two-phase nano-metal composites under pressure-assisted sintering is essential for the development of advanced chip-interconnection materials. However, a significant challenge remains in decoupling the effects of sintering parameters and quantitatively linking process conditions to the mechanical performance of sintered structures at the atomic scale. In this paper, we employ a multi-step molecular dynamics approach to systematically investigate the sintering kinetics and mechanical responses of two-phase nano-metal composites under pressure-assisted sintering. We reveal how the synergistic interaction between the constituent phases and the multi-stage sintering process collectively governs the sintering performance and mechanical properties of the composite system. Our results demonstrate that sintering pressure, temperature, and phase ratio critically regulate the sintering kinetics and microstructural evolution. Specifically, external pressure acts as the primary driver for particle rearrangement and atomic diffusion, while thermal activation facilitates atomic migration across interfaces. The softer metal phase introduces extensive stacking faults and dislocations, significantly enhancing diffusion pathway connectivity. Furthermore, the mechanical properties of the sintered body are influenced by both the intrinsic characteristics of the constituents and the resulting sintered microstructure. Through modulating the two-phase ratio, the fracture mode can be shifted from single-phase-dominated to a multiphase-coordinated mechanism. We proposed a novel qualitative competitive model to rationalize the mechanical performance of the composite, which conceptually integrates the intrinsic properties of the constituent metals with the achieved degree of densification. This work provides fundamental insights into the microstructure-property relationship of two phase nano-metal composites during sintering and offers a theoretical basis for designing materials with tailored strength and damage tolerance.

The active heat dissipation technology of SiC power modules based on thermoelectric effect has been proven to be able to suppress chip temperature fluctuations and improve system reliability. However, the long heat dissipation path and thermal resistance limit the further improvement of the cooling performance of the power module. In this paper, an innovative in-situ high-efficiency thermal management technology for power module driven by thermoelectric effect was proposed. By directly integrating the thermoelectric cooler (DI-TEC) with power chip, the multi-layer heterostructure is removed, greatly shortening the heat conduction path. The DI-TEC module has excellent heat dissipation capability and temperature uniformity performance in synergy. A module structure optimization strategy was proposed, which can greatly improve the cooling performance of the module by regulating the number of thermoelectric semiconductors. The excellent mechanical properties of the DI-TEC module were verified through thermodynamic simulation. The experiment compared the junction temperature data of conventional DBC module and DI-TEC module. At high power density, this near-junction heat dissipation scheme can reduce the chip junction temperature by 47.58 degrees C, with a cooling ratio of up to 44.88%. Furthermore, the DI-TEC module enables concurrent optimization of both junction temperature control and thermal homogeneity through a single actuation signal. While achieving peak cooling performance, the module maintains a 50.50% enhancement in temperature uniformity across multiple chips. This module has the potential to reduce the probability of thermally induced failures and extend the service life of the module. This revolutionary breakthrough has enormous potential in the field of thermal management for high-density power electronics.

The dynamic current imbalance between the paralleled SiC MOSFETs in multichip power modules, which is commonly attributed to the asymmetric module layout, severely limits their current capacity and thermal reliability. Adjusting the connection points of bonding wires is an effective method to mitigate imbalanced dynamic current. However, manual trialand- error is currently the most common method for optimizing connection points, which is both deficient and inefficient. Existing automated solutions usually rely on a prefitting process based on large datasets, which is time-consuming and impractical for highdimensional parameter applications. Thus, this article proposes an optimization model to mitigate dynamic current imbalance, which can automatically adjust the connection points of bonding wires without any manual intervention. The Reinforcement Learning (RL) Soft Actor-Critic (SAC) algorithm was applied to the power module optimization, eliminating the need for prefitting and enabling high-dimensional parameter optimization. After optimization, nearly complete dynamic current balancing in both high-side and low-side switches in a multichip-paralleled half-bridge power module is achieved, as verified by simulations and experiments. This model achieves true dynamic current balancing automation for the first time, providing an important reference for the application of RL to the automated optimization of multichip power modules.

Mismatched parasitic parameters between the paralleled branches cause gate oscillation, which can lead to severe electromagnetic interference (EMI) and may even evolve into self-sustaining oscillation. Therefore, it is significant to reveal the mechanism of parallel oscillation and analyze the influence of parameters. However, the gate oscillation induced by the mismatched parameters of the freewheeling branches has not been thoroughly investigated. To address this issue, the oscillation excitation and conduction models incorporating the freewheeling branches are established. Based on the models, the influences and effect mechanisms of the differential parameters (LdH and LsH) and common parameters (LdH, LsH, LkH, Lac, LdL, LsL, LkL) on the magnitude of oscillation excitation and the gain of oscillation conduction are analyzed. Furthermore, by coupling the two models, the effect directions and degrees of the common parameters on the magnitude of parallel oscillation are investigated. Finally, all conclusions are well validated through experiments, and their contributions to the circuit layout design are discussed.

With the development of electric vehicles (EVs), the demand for high-efficiency, high-power-density on-board chargers (OBCs) is increasing. Traditional OBCs utilize a two-stage structure, which limits their efficiency and power density. Single-stage AC-DC topology has greater development potential due to their high efficiency, high power density, and the absence of large-capacity electrolytic capacitors with short life span. This paper designs a high-efficiency, high-power-density, 3.3kW single-stage OBC using SiC and GaN devices. The advantages and disadvantages of different magnetic integrated transformer using Litz wire windings are analyzed and compared, and a magnetic integrated transformer with high winding area utilization and low proximity effect losses is proposed. To address the large air gap in the resonant inductor which will cause large eddy current losses, a distributed air-gap magnetic circuit is designed to reduce eddy current losses. Finally, an experimental prototype with a peak efficiency of 97.97% and a power density of 8.14kW/L is designed to validate the effectiveness of the proposed magnetic integrated transformer.

The three-level (3-L) simplified neutral point clamped inverter featuring a reduced transistor count represents a promising alternative for a three-phase inverter system. However, when applying conventional modulation methods, the switching losses of the 2-L inverter stage remain high, and increase significantly under nonunity power factor conditions. To address this issue, a novel space vector pulse width modulation method based on zero vector transitions is proposed in this letter. The proposed method achieves zero switching loss of the 2-L inverter stage devices. The performance of the proposed modulation method is presented using a 1.5-kVA hardware prototype. The proposed method achieves a significant efficiency improvement over a wide power factor range, with an increase of 0.2% at resistive load (PF = 1) and 0.5% at inductive load (PF = 0.7) compared with the conventional low-switching-loss modulation method.

The totem pole power factor correction (PFC) circuit is a prevalent front-end topology employed in on-board chargers owing to its high efficiency and uncomplicated structure. Nevertheless, the conventional fixed parameters control methods are deficient in terms of robustness, resulting in high total harmonic distortion (THD) of input current when operating over a wide voltage range. To solve this problem, this article first proposes a dynamic root locus PI control based on the small signal model analysis of totem pole PFC. Furthermore, a dual-frequency adaptive PI control based on back propagation neural networks (DF-BPPI) is proposed for optimization of the control parameters. Compared to existing methods, the proposed control method can achieve lower current THD under different output voltages and loads. Experimental results on a 3-kW prototype demonstrate that the proposed DF-BPPI control attains a THD of less than 3% and a power factor higher than 0.995 under all output voltages above half load.

SNPC(Simplified Neutral Point Clamped) topology as a promising three-level converter topology, implementing such a topology using existing commercial power module inevitably leads to significant parasitic inductance, which limits its further development. So it is necessary to integrate the entire topology within a single module. In this paper, a power module for the SNPC topology is designed. By independently optimizing the commutation loops of the former stage and latter stage, an overlapped busbar structure is introduced to reduce the difference in parasitic inductance between different phases. The proposed module design is validated through simulation and experiments.

Silicon carbide (SiC) devices operate at higher switching speeds and frequencies than traditional silicon (Si) devices, and also generate more significant common-mode (CM) electromagnetic interference (EMI). Integrated EMI filters within the power module offer better performance than external filters above 10 MHz. But the existing integrated design still suffers from insufficient filtering performance below 10 MHz and high core losses in the CM inductors due to the parasitic inductances and terminal placement. To address these problems, this paper presents a novel integrated EMI filter structure within the SiC power module. Featuring a low-leakage stripline inductor and additional terminals, it enhances EMI suppression over a wider frequency range and effectively reduces the core losses. A frequency-domain analysis model is developed to analyze the impact of key parasitic parameters from 150 kHz to 30 MHz, addressing gaps in current theoretical analysis. Based on this, the proposed EMI filter structure is introduced. A power module prototype employing this structure is fabricated, and an EMI test bench is constructed. Experimental results from 150 kHz to 30 MHz demonstrate that the proposed structure achieves superior filtering performance to the existing structure, and also achieves a 10 dB improvement compared to the external filters.

Understanding the densification mechanisms and mechanical failure behavior of trimodal-sized nano-metal materials under pressure-assisted sintering is critical for developing high-reliability interconnects in advanced power electronics packaging. This paper presents a systematic atomic-scale investigation using multi-step molecular dynamics simulations to reveal the underlying mechanisms by which multimodal architectures govern sintering kinetics and mechanical performance. Results demonstrate that pressure drives atomic migration, while medium and small particles fill interstices between large ones, forming hierarchical structures. Temperature complements pressure, with thermal activation dominating at high temperatures to achieve dense states. During uniaxial tension, the system with a high proportion of small-sized particles exhibits excellent strength. Pressure-driven pore closure enhances Young’s modulus, while the fine particles sintered at triple junctions and interstitial sites form a continuous, densely packed network that physically constrains the motion and deformation of the larger particles during tensile loading. This work established a comprehensive mechanistic understanding of how trimodal particle size distributions govern sintering densification and mechanical failure in nano-metal systems, offering fundamental design criteria for tailoring mechanical properties including strength, toughness, and damage tolerance.

The three-phase three-level (3-L) simplified neutral point clamped (SNPC) inverter features a reduced device count, compared to the typical 3-L topologies, representing a promising alternative for photovoltaic inverters and motor drive systems. In these applications, common-mode (CM) voltage has severe negative effects and therefore should be reduced. However, conventional CM voltage suppression methods for SNPC inverter typically result in high-switching losses of the 2-L inverter stage devices. To address this issue, a novel CM voltage suppression method with zero-voltage switching (ZVS) of the inverter stage devices is proposed in this article. The modulation sequence is optimized to reduce CM voltage amplitude to V-DC/6 and achieve ZVS of the inverter stage devices. The space vectors dwell-time calculation is provided, and an adjusting parameter is introduced, which influences the zero vectors dwell-time. Furthermore, the DC-link mid-point voltage is balanced through two pairs of virtualized small vectors. Finally, experimental validation on a 1.5-kVA hardware prototype demonstrates that the proposed method effectively suppresses the CM voltage while maintaining mid-point voltage balance and improves efficiency by 0.4% under resistive load (power factor (PF) = 1) and by 0.9% under inductive load (power factor (PF) = 0.7) compared with the conventional CM voltage suppression method.

The double-sided cooling (DSC) power modules are sandwich packaging with more soldering interfaces, which suffer higher thermal-induced stress than traditional wire-bonding packaging. Considering reliability and thermal conductivity, state-of-the-art spacers were implemented as a buffer to lower the stress. This article introduced a spacer made of direct-plated copper (DPC) with vias to reduce the thermomechanical stresses in the DSC power module. The DPC-via-spacer (DVS) consists of aluminum nitride (AlN) ceramic with close coefficients of thermal expansion (CTE) to SiC devices and copper layers with stressstrain relieved edge design. Single-switch DSC modules with copper spacer, molybdenum spacer, and DVS were designed and fabricated. Simulation results showed that, at a power loss of 90 W, the thermally induced strain at the most vulnerable solder layer of the module with the DVS was reduced by 80% compared to that of the module with the copper spacer. Compared with the Mo spacer, the junction temperature is reduced by 4% under a similar stressstrain behavior. Considering skin effect under 500-MHz frequency, the electrical resistance of the DVS is 92.6% and 50.5% of that of the copper spacer and the Mo spacer, respectively. Power cycling test results showed that the lifetime of the modules with DVS is 50% and 20% longer than that of the modules with copper spacer and Mo spacer, respectively. The results prove that DVS can reduce the thermomechanical stressstrain on the solder layer and enhance the reliability of the power module.

The three-phase three-level (3-L) sparse neutral point clamped (SNPC) inverter features a reduced number of power semiconductor devices, compared to the classical 3-L NPC and T-type inverters, representing a promising alternative for industrial motor drives and electric vehicle traction systems. However, the switching losses of the 2-L inverter stage increase significantly under nonunity power factor condition when applying conventional sequences, resulting in reduced efficiency. To address this issue, a novel space vector pulse width modulation method based on zero vector transitions is proposed in this article. The proposed sequence achieves zero-voltage switching of the 2-L inverter stage devices. Thus, the switching losses of the 2-L inverter stage can be theoretically eliminated. Furthermore, the dwell-time calculation of the vectors is reconsidered, and an adjusting parameter is introduced, which influences the differential-mode and common-mode (CM) voltage-time area ripples. Finally, experimental validation on a 1.5-kVA hardware prototype demonstrates that the proposed method achieves higher efficiency over a wide power factor range, with a 0.3% increase at inductive load (PF = 0.7) and a 0.35% increase at capacitive load (PF = 0.65) compared with the conventional low-switching-loss modulation method. Meanwhile, the proposed method generates lower CM voltage-time area ripple over a wide modulation index range, which is further verified by CM current measurements.

The lack of a unified understanding linking pressure-assisted sintering manufacturing conditions with anisotropic mechanical response and failure behavior in metallic nanowire interconnects limits their rational design in advanced power electronic devices. Here, a continuous molecular dynamics framework was developed to establish a direct correlation between sintering parameters, microstructural evolution, and mechanical performance of metallic nanowires. The results reveal a pronounced size-dependent crystal transformation, where small-diameter nanowires undergo diffusion-driven amorphous-to-FCC recrystallization, whereas larger nanowires exhibit FCC-HCP transitions governed by partial dislocation activity and stacking-fault confinement, indicating a shift in dominant sintering kinetics. External pressure and temperature further regulate these transformations by modulating atomic mobility and defect evolution, thereby determining whether recrystallization or defect accumulation dominates structural evolution. The sintered nanowires show strong mechanical anisotropy, with higher Young's modulus along the Z direction than the X direction due to efficient axial load transfer along continuous nanowire backbones versus interface-controlled deformation at sintering necks. In addition, failure modes are tunable from neck-dominated fracture to planar fracture with increasing densification, establishing a clear linkage between manufacturing conditions, elastic response, and fracture behavior. Overall, this work provides a unified atomistic framework for understanding and engineering structure-property relationships in sintered metallic nanowire networks.

With the development and promotion of renewable energy sources such as solar and wind, efficient energy storage systems are becoming increasingly important in the mix. Bidirectional DC/DC converter is a key device for energy conversion between battery bank and DC bus, which directly affects the efficiency, power density and reliability of the system. However, conventional single-phase CLLC converters face limitations in high-power applications, where large magnetic components restrict performance improvement. In this paper, a three-phase interleaved bi-directional CLLC converter with vertically integrated magnetic components is proposed, which utilizes a three-phase interleaving technique to connect three CLLC converters in parallel with a phase shift of 120°, resulting in a reduction of current ripple and an increase in power rating. Meanwhile, the integration of all inductor and transformer cores in the converter can realize magnetic flux offset, reducing core loss and component size. In this paper, a symmetrical three-phase perpendicular magnetic integrated structure is designed by analyzing its magnetic reluctance model, and the core and winding losses are reduced by optimizing the geometrical parameters in order to minimize the losses and volume. Validated by simulations in MATLAB/Simulink and ANSYS Maxwell, this design reduces core losses by 39

Conventional press-pack insulated-gate bipolar transistor (PP-IGBT) devices suffer from significant contact thermal resistance, which can account for up to 50% of the total thermal resistance, leading to elevated junction temperatures and severe thermal non-uniformity. Although the double-sided sintered silver scheme can reduce thermal resistance, it still suffers from high cost and high porosity in large-area sintering, as well as solder-layer cracking and stress concentration under high clamping force. To address these issues, this paper proposes a low-thermal-resistance press-pack power module packaging structure based on the synergistic heat dissipation using graphene film (GF) and sintered nanosilver. This structure fully utilizes the high in-plane thermal conductivity of the flexible GF and the stress-buffering properties of the nanosilver to achieve optimal thermo-mechanical performance. Furthermore, an integrated hot-pressing process for flexible GF is proposed, achieving intimate interfacial contact and eliminating the need for large-area sintering, thereby simplifying manufacturing and assembly. Simulation and experimental results indicate that, compared with conventional approaches, the proposed structure reduces the maximum junction temperature, chip's in-plane temperature non-uniformity, and junction-to-case thermal resistance by 16.06%, 51.87%, and 25.39%, respectively, while maintaining excellent thermo-mechanical performance over a wide range of power levels and clamping forces. In addition, power cycling tests verify its long-term reliability.

High thermal conductivity two-dimensional nanosheets have been proven to enhance the thermal performance of nano metal die-attach materials. Due to the weak affinity between metal nanoparticles and nanosheets, the improvement of mechanical properties of die-attach materials is greatly limited. In this paper, we proposed a strategy of introducing nanoscale surface defects on the surface of two-dimensional nanosheets to induce longitudinal sintering of nanoparticles, achieving ultra-high sintering and mechanical properties of nano-Cu based composite. Using two-dimensional BN nanosheets as an illustrative example, we conducted molecular dynamics (MD) simulations to reveal the influence of surface defects on induction effect. Furthermore, we examined how the location, arrangement mode, geometric size, and shape of surface defects contribute to enhancing the mechanical performance of composites. Our findings indicate that surface defects that are aligned can inhibit the alternating deformation of BN nanosheets between high and low states, and mitigate damage to the crystal structure of composite by decreasing material interactions. Sintering neck that penetrates the surface defects holds a pivotal position in bolstering the mechanical attributes of composites. By adjusting the longitudinal interconnection and minimizing the interactive squeezing effect, an increase in surface defect induction points can achieve ultra-high mechanical properties of composites. Altering the geometric dimensions of surface defects can adjust the underlying competitive relationships between constraints and gap wrinkles in the deformation of BN nanosheets. In addition, surface defects consistent with the sintering neck morphology can achieve the best mechanical properties of the composite. This work provided an effective method for designing and optimizing high thermal conductivity and high-strength nano-Cu based die-attach materials.