The reliability of insulated gate bipolar transistor (IGBT) module is predominantly affected by the aging of their internal bond wires. Based on this, this paper proposes a non-invasive aging monitoring method for power device bond wires in three-phase two-level inverters. The lift-off of bond wires increases parasitic inductance within the power circuit, disrupting the parameter balance of the three-phase bridge arms and causing an increase in the characteristic dip of the neutral-point voltage's frequency response. The proposed method monitors the frequency-domain response of the system's neutral-point voltage. Specifically, it uses the magnitude of the dip at the switching frequency in this response as an indicator for assessing the health state of the IGBT module. Results demonstrate that this characteristic dip exhibits a consistent positive correlation with the extent of bond wires lift-off. Furthermore, the indicator is minimally influenced by temperature and instantaneous current, enabling reliable monitoring across various DC bus voltages and load conditions.
The All Solid-State Transmitter (ASTRAM), currently being developed at the Jet Propulsion Laboratory in Pasadena, offers an alternative to traditional tube-based microwave sources. To ensure stable gain and efficient power combining, precise temperature control of the Monolithic Microwave Integrated Circuit (MMIC) power amplifiers is essential. However, fluctuations in the temperature of the water used to cool the MMICs — caused by imprecise chiller output — result in variations in the MMIC channel temperature. This induces fluctuations in the output RF power of the amplifier. To address the impact of changing water temperature and ambient conditions, we have implemented a temperature control system using a hybrid-cooling approach where liquid cooling carries bulk of the heat and a thermoelectric cooler (TEC) provides the necessary additional cooling or heating to stabilize the MMIC channel temperature. A PID (Proportional-Integral-Derivative) controller, paired with a thermocouple to measure the MMIC temperature, has been utilized to control the TEC. Experimental tests with the PID controller demonstrate 93% improvement in rms MMIC temperature fluctuations and 64% improvement in rms RF power fluctuations.
Compared with conventional integrated interconnection technologies, through glass via (TGV) interconnection structures, benefiting from smaller package dimensions, excellent electrical performance, and favorable thermal stability, are regarded as one of the most promising interconnection solutions for advanced 3D packaging. However, during practical service, the mismatch in coefficients of thermal expansion (CTE) between heterogeneous material interfaces gives give rise to significant thermomechanical incompatibilities in TGV structures when subjected to cyclic thermal loading, which promote the development of high localized thermal stresses. Such thermally induced stresses give rise to pronounced cyclic displacement and volumetric contraction in the copper filled vias, thereby accelerating structural degradation and shortening the service lifetime of electronic devices. To address these issues, this study integrates crystal plasticity theory into finite element simulations to establish a two-dimensional polycrystalline copper TGV numerical model that explicitly accounts for grain size effects. Under thermal cycling conditions, the influences of grain number and sidewall tilted angle on the deformation behavior and damage evolution of TGV-Cu are systematically investigated. The results indicate that an increase in grain number leads to more pronounced stress and deformation localization within the structure, which in turn elevates the creep strain rate and accelerates service degradation. In addition, the sidewall tilted angle is found to have a significant impact on the fatigue lifetime of TGV structures. Larger tilted angles induce more severe pumping and shrinkage deformation, thereby markedly deteriorating the thermal stability and service reliability of TGV interconnects in high-power electronic devices.
The impact of manufacturing tolerances on the electromagnetic performance of frequency selective surfaces (FSS) is investigated through a physically grounded scaling-based framework. Fabrication tolerances T introduce independent variations in the outer dimensions and conductor width, producing non-uniform geometric perturbations that are amplified in the smallest regions of the unit cell. Since the resonant behavior of FSS structures is governed by these critical features, such perturbations lead to measurable shifts in the resonance frequency, expressed as a relative deviation Δf. A systematic set of full-wave simulations covering multiple FSS geometries, operating frequency bands, and tolerance levels was used to investigate the relationship between fabrication accuracy and resonance-frequency deviation. When analyzed in terms of the normalized parameter T/w, where w denotes the conductor width, results from different geometries and frequency bands collapse onto a linear trend. This behavior is described by the relationship Δf(%)≈ 40 ∙(T/w), obtained through regression analysis of the complete dataset, providing a compact tolerance-performance model that captures a common scaling trend across the analyzed FSS geometries. The proposed formulation links fabrication-induced geometric perturbations to RF performance and enables direct estimation of allowable manufacturing tolerances from performance specifications. The resulting framework supports tolerance-aware design and facilitates the selection of suitable manufacturing technologies based on fabrication capability and electromagnetic performance requirements.
Additive manufacturing (AM) of metallic structures directly on active metal brazed (AMB) substrates enables adhesive-free interconnects for advanced power module packaging and high-aspect-ratio three-dimensional interconnect architectures. Copper (Cu) and aluminum alloys are attractive material systems; however, selective laser melting (SLM) introduces thermomechanical stress, porosity, surface roughness, and oxidation that degrade electrical performance and impose manufacturing challenges. In this work, Cu and AlSi10Mg pillar structures were fabricated by SLM directly on Si₃N₄-based AMB substrates and evaluated for substrate warpage, mechanical integrity, and electrical transport. Cu pillars induced significantly higher substrate bow than AlSi10Mg for comparable printed volumes, while exhibiting stronger metallurgical attachment. Asprinted pillars showed elevated electrical resistance dominated by interfacial effects. Four-point probe measurements showed that electroless silver (Ag) metallization followed by moderate annealing reduced resistance by approximately 41% in Cu and 36% in AlSi10Mg pillars, while improving electrical stability. Overall, this study identifies interfacial resistance as the dominant limitation of printed current-carrying structures and demonstrates that combining electroless Ag metallization with moderate annealing effectively mitigates it. This hybrid additive-manufacturing and post-processing strategy enables mechanically robust, low-resistance, adhesive-free high-aspect-ratio interconnects integrated directly on AMB substrates, offering a route beyond conventional solder and wire-bond interconnection for next-generation power module packaging.
Low-temperature Cu–Cu bonding is critical for glass-based 3D advanced packaging, as conventional high-temperature processes induce severe thermal stress via CTE mismatch. This work investigates Ti-passivation-assisted low-temperature Cu–Cu bonding through molecular dynamics simulations and experimental characterization. The results reveal that the Ti layer spontaneously undergoes solid-state amorphization (SSAR) under coupled thermodynamic and kinetic effects: negative Cu–Ti mixing enthalpy drives intermixing, while rapid asymmetric interstitial diffusion of small Cu atoms induces lattice distortion and structural collapse. The resulting amorphous layer acts as an ultrafast diffusion channel with reduced activation energy, enabling dense bonding at 200 °C with >90 % wafer-level effective area and 16 MPa tensile strength. Failure occurs at the glass/Ti film–substrate interface rather than the bonded Cu–Cu interface. These findings provide mechanistic insights and a viable pathway for reliable multilayer glass stacking in high-performance 3D packaging.
Two-phase immersion cooling is an emerging thermal management technology for high-performance computing, offering superior heat dissipation compared to conventional air cooling. However, prolonged immersion has been associated with contamination deposition at ball grid array (BGA) interfaces, leading to electrochemical migration (ECM), dendrite formation, and electrical shorting of integrated circuit (IC) packages. This study investigates IC package edge-bonding as a mitigation strategy to reduce contamination deposition at BGA solder joints in a two-phase immersion cooling environment. An accelerated stress test was conducted over a 42-day period using ten compute servers equipped with field-programmable gate array (FPGA) accelerator cards immersed in a fluorocarbon-based dielectric fluid (FC-3284). Seven FPGA cards received edge-bonding treatment while three remained untreated as controls. Thermal stress was applied continuously at thermal design power (TDP) levels to maximize boiling and contamination deposition. Post-test evaluation employed X-ray fluorescence (XRF) spectroscopy with elemental mapping, using bromine (Br) as a signature contaminant marker. Edge-bonded samples demonstrated a bromine reduction of 89.3% (Cu-calibrated) and 90.2% (Sn-calibrated) compared to controls. Edge-bonding is confirmed as a highly effective protective measure, though it does not entirely eliminate contamination ingress. These findings have significant implications for reliability engineering of immersion-cooled data center hardware.
A flexible bandstop frequency selective surface (FSS) is designed and fabricated using a 3D-printed thermoplastic polyurethane (TPU) 87A. The structure is realized through copper foil on a substrate of 1.2 mm thickness. Experimental validation confirms a stopband response from 5.01 to 9.61 GHz, with minimal performance degradation under mechanical bending. The symmetric geometry ensures polarization insensitivity, while stable frequency characteristics are maintained for oblique incidence angles up to 75°, making it suitable for practical applications. The combination of mechanical flexibility and angular stability supports applications in conformal electromagnetic shielding. An equivalent circuit model is integrated with deep learning to improve prediction accuracy. Compared to benchmark modeling approaches such as Deep Neural Network (DNN), K-Nearest Neighbors (KNN), Support Vector Regression (SVR), and Extreme Gradient Boosting (XGB). The proposed Radial Basis Function Neural Network (RBFNN) based optimization achieves superior computational efficiency, model compactness, and enhanced generalization. The proposed approach demonstrates the potential for next-generation flexible and conformal electromagnetic surfaces through advanced manufacturing and computational optimization.
As high-performance computing (HPC) technology advances to provide the computational power and data management needed to train sophisticated artificial intelligence (AI) models, the demand for higher current and power continues to rise. The escalation in power requirements presents new challenges for the design and implementation of power distribution networks (PDNs). Conventional lateral power delivery architecture (LPD) with voltage regulars (VRs) placed on same side of die results in longer routing path between the VR output and load circuits and correspondingly higher power dissipation. Vertical power delivery (VPD) architecture, on the other hand, places VRs on backside of printed circuit board (PCB) to shorten the routing distance. This article focuses on the power integrity challenges and design optimizations to reduce voltage noise within a VPD architecture. Capacitor types and placements, package (PKG) and PCB optimizations, and load current characteristics are explored to mitigate voltage drop on the die side. Simulation data based on practical industrial applications reveals more than 20% normalized voltage drop improvement with optimized capacitor scheme and approximately linear relationship between voltage drop and load current profile. In addition, this work identifies a VPD-specific architectural trade-off, showing that partial VR alignment improves system-level PDN performance by enhancing PCB decoupling effectiveness, despite reduced VR proximity.
Flip-chip packaging enables high-speed transmission and high I/O density for DDR memory devices. Within-wafer bump height uniformity and intra-die coplanarity (COP) directly determine interconnect reliability, and electroplating is the critical fabrication step. Conventional optimization approaches, such as plating parameter tuning and dummy bump layout, suffer from lower throughput, greater design complexity, and wasted effective die area. Most existing studies focus on separate flow or electric field regulation, whereas systematic experimental investigations integrating multiple flow field components to realize synergistic flow–electric field co-regulation are limited for mass-produced 12-inch DRAM wafers with mixed support–function bump structures. This work proposes a hardware optimization route to simultaneously mitigate central ion accumulation and wafer-edge electric field crowding. Iterative copper pillar and solder electroplating experiments were carried out on an ACM Ultra ECP platform using 12-inch flip-chip DRAM wafers with 764 valid dies per wafer. The regulation performance of three core components (diffusion plate, edge shield, and reciprocating stirrer) on bump uniformity and COP was systematically explored. Following the IPC-7095 specification, max-min COP within each die is adopted, with dual evaluation thresholds: COP > 10 μm as the mass-production rejection limit and COP > 8 μm as a tightened reliability criterion. After full-dimensional flow field optimization, the maximum wafer-level bump height deviation decreased from 7.7 μm to 5.44 μm. The optimized Leg5 condition yields zero dies with COP > 10 μm (100% production yield) and only one die with COP > 8 μm (99.87% reliability yield). Repeatability tests on six wafers confirm stable performance. The proposed method maintains plating current density without dummy bumps, filling a domestic research gap in flow-field regulation for flip-chip mixed-bump electroplating. The established hardware scheme and process window can be deployed directly on DDR flip-chip packaging lines, supporting independent advanced memory packaging technology and offering a reference for bump electroplating optimization of other advanced packaging devices.
This study concentrated on the design and fabrication of a mini cooled optical assembly (OSA), exhibiting excellent wavelength and linewidth stability in a wide temperature range of −50 °C to 90 °C. The OSA was based on a mini box package with a compact housing size of 8.7 mm × 6.65 mm × 5.3 mm. The optical output used polarization-maintaining fiber (PMF), and two key innovative structural elements were integrated into this OSA. Firstly, the micro-thermistor was placed directly on top of the laser chip to achieve strong thermal coupling. Secondly, a bridge-type wire-bonding configuration was adopted to suppress thermal interference from the bonding wires. Finite-element thermal simulations performed in Ansys showed that this design could reduce the temperature difference between the thermistor and the laser junction from 3.6 °C in the conventional structure to 0.3 °C, significantly improving the temperature-sensing accuracy of the thermoelectric cooler (TEC) control system. This OSA could maintain a power output greater than 40 mW and a linewidth of less than 100 kHz across the temperature range of −50 °C to 90 °C. Additionally, 12 OSA devices were manufactured, and their wavelength stability under high- and low-temperature environments was considered. The results indicated that this design ensured a wavelength drift below 30 picometers. This method provided a low-cost, integration-friendly solution for wavelength and linewidth stabilization, demonstrating its suitability for precision optical communication and sensing applications.
With the trend towards miniaturization and high-density integration in electronics, the demand for precise protection of printed circuit board (PCB) assemblies has become increasingly critical. Traditional liquid conformal coatings, while widely used, face challenges such as complex application processes, poor thickness uniformity, and excessive space requirements. These limitations make them less suitable for next-generation electronic packaging. This paper presents the design, fabrication, and characterization of a novel, highly deformable, dual-layer conformal coating film applied via a vacuum lamination process. The film consists of a fully-cured protective layer and a B-stage (semi-cured) adhesive layer. A thermoplastic polyurethane (TPU) was crosslinked with different isocyanates to investigate the influence of polymer structure on the mechanical properties and conformality of the protective layer. The developed protective layer exhibits an exceptional elongation at break of 670% and an elastic modulus of 42 MPa, ensuring complete coverage over complex topographies without defects. The adhesive layer provides excellent gap-filling capabilities and strong adhesion. Furthermore, the study examined the influence of the protective layers with different mechanical properties on the failure mode when laminated to PCBs and electronic components. This investigation offers valuable insights for the design and optimization of conformal coating films in electronic protection applications. The fabricated 100 μm dual-layer film demonstrated outstanding conformality on test PCBs, achieving a final thickness of 15-25 μm over components. It exhibited good electrical insulation with a volume resistivity of 5.81×10¹² Ω·cm and excellent adhesion (Class 5B per ASTM D3359-17) to copper, polyimide and solder mask ink substrates. Furthermore, the film maintained its insulation and adhesion ability after reliability tests, including thermal shock (-40°C to 125°C) and high temperature/humidity (85°C/85% RH) test. These results indicate that the developed dual-layer conformal film is a highly promising solution for providing reliable and efficient protection for modern high-density electronic devices.
This work presents a novel method for preparing seamless three-dimensional (3D) interconnects in bump-less 3D integrated systems through a one-step electroplating process at room temperature (25°C). This method was demonstrated using a three-layer chip stack. Copper (Cu) pillars within the through-silicon vias (TSVs) and interlayer Cu interconnects were simultaneously formed by room-temperature electroplating. Three chips were bonded by permanent bonding adhesive. After all micro-channels were sufficiently immersed in a copper sulfate electroplating solution, copper electroplating enabled the monolithic fabrication of 3D interconnects. Furthermore, no original interfaces, IMCs, apparent voids, and cracks were observed in the 3D copper interconnects. The measured direct current resistance of the formed 3D copper interconnects was very close to the theoretical value. Electrical measurements at 25°C and 80°C and after 50 thermal cycles from 0°C to 80°C showed stable resistance behavior under the tested conditions. The seamless pure 3D copper interconnects are very valuable for high-quality 3D integrated systems.
This paper proposes a novel low-temperature curable multi-permeability (LTCMP) toroid core fabricated by applying precisely controlled, variable compaction pressure during formation to individual rings requiring a specific permeability. This targeted manufacturing approach enables the permeability of the final core to increase discretely along the radial direction, thereby achieving a significantly more uniform flux density distribution throughout the core structure compared to conventional single-permeability designs. Theoretical electromagnetic calculations and comprehensive finite-element analysis (FEA) simulations were rigorously employed to evaluate and validate the performance characteristics of the multi-permeability cores. Moreover, the inductance behavior and core loss density under specified operating conditions were experimentally characterized and compared for both a representative LTCMP core and a baseline single-permeability core.
The post-Moore era has ushered in the development of multi-chip and multi-stack chiplet-based systems, with hybrid bonding (HB) serving as a method to achieve ultra-fine pitch interconnections. This paper presents a scalable stress recovery technique designed for thermal-mechanics analysis of hybrid bonding. Our method enhances the accuracy of C-1 continuous stress on element boundaries within finite elements by employing post-processing on the displacement-based finite element method (FEM). This recovery technique focuses solely on solving local problems near the finite element, making it well-suited for deployment in multi-core parallel application scenarios. We illustrate the effectiveness of this approach through numerical examples involving chip-to-wafer (C2W) and die-to-wafer (D2W) HB cases, analyzing its accuracy, efficiency, and scalability. Overall, our method demonstrates advantages over traditional approaches, achieving a 90.9% reduction in computational scale, a 95.4% decrease in running time, and a 44.5% reduction in memory usage, all while maintaining the same accuracy requirements. Furthermore, we evaluate the thousand-core parallel capability of this technique on a high-performance computing (HPC) platform, underscoring its application in simulating ultra-high density chiplet interconnections, and evaluating the potential risk of bonding voids from simulation.
This paper proposed a new design of self-packaged two-port reflectionless bandpass filter (RBPF) based on the substrate integrated waveguide (SIW). The working mechanism of the RBPF is first addressed, which is constructed in balanced-circuit form by two central symmetric phase-shifting filtering networks and two power dividers/combiners at the two ports. Specifically, the reflectionless filtering network mainly consists of a phase-shifting stripline-to-SIW transition and an SIW-based bandpass filter (BPF). The unwanted reflected signals within the stopband of the reflective SIW BPF are absorbed by the isolation resistors of the Wilkinson-type power divider/combiner, which achieves a two-port reflectionless behavior. For validation, a self-packaged RBPF prototype is fabricated and measured, showing good agreement between the measured and simulated results. The experimental results illustrate that the RBPF centered at 9.91 GHz with a 3-dB fractional bandwidth of 7.3%. Excellent two-port reflectionless performance is attained over the frequency range of 5.07–14.96 GHz which covers all X-band, with a -10 dB reflectionless fractional bandwidth of 98.75% and reflectionless range relative ratio of 2.95:1.
Microencapsulated phase change material (MEPCM) slurries can enhance liquid cooling by increasing the apparent heat capacity of the working fluid through latent heat absorption. However, in straight microchannels, limited transverse mixing under low-Reynolds-number flow restricts MEPCM particle melting and reduces latent heat utilization. This study numerically investigates herringbone microchannels as a passive mixing strategy to improve MEPCM slurry heat transfer for microscale thermal management. The herringbone ribs induce secondary vortical motion and enhance cross-sectional temperature uniformity, promoting more effective MEPCM melting while introducing an associated pressure-drop penalty. A parametric study is performed over herringbone height, nominal rib thickness, Reynolds number, and MEPCM volume concentration, and regression-based correlations for Nusselt number and friction factor are developed for multi-objective optimization using NSGA-II. The optimized herringbone microchannel with a water-based MEPCM slurry achieves a heat transfer coefficient of 7.3×104 W/m2.K with a pressure drop of 37.9 kPa for the selected balanced design case. This corresponds to a ∼ 3.8× enhancement over straight microchannels with MEPCM slurry and a ∼ 1.6× enhancement over herringbone microchannels with single-phase water, demonstrating the combined benefit of herringbone-induced mixing and latent heat utilization.
This study presents an efficient simulation methodology based on the corrected First-order Shear Deformation Theory (FSDT) to address process-induced thermal stress in deep trench capacitors (DTCs) arising from complex thermal processing. This approach overcomes the computational distortion and numerical instability inherent in conventional three-dimensional elasticity theory when applied to ultrathin, high-aspect-ratio dielectric films. Focusing on the Al2O3–HfO2–Al2O3 composite dielectric layer, the FSDT formulation is modified to account for strain calculation errors associated with the non-planar geometric features at the DTC sidewalls, substrate, and corner regions. A systematic comparative analysis of stress distributions is conducted across film thicknesses ranging from 9 nm to 60 nm. The results demonstrate that three-dimensional elasticity theory offers superior capability in capturing transverse normal stresses for relatively thick films (e.g., 60 nm), whereas for ultrathin films (10 nm and below), conventional three-dimensional models exhibit significant deviations due to excessively high element aspect ratios. In such regimes, the corrected FSDT effectively circumvents mesh failure and yields physically consistent stress predictions. In conclusion, the corrected FSDT computational framework established herein provides essential theoretical foundations and technical support for the thermal stress analysis and process reliability optimization of ultrathin DTC structuresfor advanced 2.5D packaging.
The prediction of thermal fatigue life for solder joints is a key aspect of reliability design in electronic packaging. Existing methods face challenges such as high barriers to traditional finite element (FE) simulation, low efficiency, and poor reusability, while purely data-driven models suffer from issues like the “black-box” nature, overfitting in small-sample conditions, and limited physical interpretability. This paper proposes a physics-guided FE surrogate Convolutional Deep Neural Network (CDNN) model that integrates a physical grouped attention mechanism with dynamic monotonicity constraints, specifically designed for high-accuracy and interpretable life prediction under small-sample conditions. Through 5-fold stratified cross-validation, the results show that the model achieves an R² of 0.8604 ± 0.0181 and an RMSE of 0.0825 ± 0.0039, demonstrating prediction accuracy comparable to Random Forest (RF) and higher than Extreme Gradient Boosting (XGBoost) and Multilayer Perceptron (MLP), while providing improved physical interpretability. Additionally, the parameters learned by the model align closely with classical thermal fatigue failure theories, providing clear physical interpretability. These findings indicate that the proposed method offers a novel technical approach to the thermal fatigue life prediction of solder joints in electronic packaging, with significant engineering potential.
