Transient thermal analysis of microstructured chip stacks requires resolving heat transport across strongly heterogeneous back-end-of-line (BEOL) interconnects while maintaining computational efficiency at the device scale. Fully resolved simulations can capture local metal–dielectric interactions but become expensive, whereas homogenized models depend on choices such as macro mesh size, representative volume element (RVE) size, and microscale boundary conditions. A laterally homogeneous layered configuration is first used to verify the transient finite element implementation against a semi-analytical multilayer heat-conduction solution. Fully resolved patterned simulations are then used as reference solutions for FE2 accuracy and cost studies. The comparison is based on temperature-amplitude responses extracted from the chip stack while varying the macro discretization, RVE size, and RVE boundary condition. The results show that the accuracy and cost of FE2 predictions are sensitive to the coupled choice of macro discretization, RVE size, and RVE boundary condition. These sensitivities are most pronounced for localized thermal responses, where the representativeness of the RVE and the imposed microscale boundary constraint have the strongest influence. The study clarifies how FE2 modeling parameters influence the balance between accuracy and computational cost in transient multiscale thermal simulations of microstructured chip stacks.
The growing demand for artificial intelligence (AI) chips and data centers has accelerated the adoption of advanced cooling technologies such as direct-to-chip liquid cooling with cold plates. However, conventional cold plate designs primarily focus on hotspot cooling with little control over heat spreading while thermal crosstalk between adjacent components remains a critical challenge in heterogeneous packages. In particular, the low thermal tolerance of memory components can make thermal crosstalk a major bottleneck. To address this, we present a thermofluidic topology optimization framework to design cold plates that minimize thermal crosstalk between application-specific integrated circuit (ASIC) and high-bandwidth memory (HBM) for various package configurations. Our algorithm optimally distributes solid material and fluid pathways within the cold plate to control conduction and convection effects based on arbitrary thermal and fluid objective functions. Consequently, the topology-optimized cold plate effectively dissipates heat from the ASIC and directs heat away from the HBM, maintaining both components within their temperature limits. For an ASIC power of 300 W, the topology-optimized cold plate with a solid volume fraction of 0.6 keeps the ASIC at approximately 90 °C and the HBM at 43 °C under a constant pumping power, corresponding to a thermal crosstalk of 0.075 °C/W, approximately one-third that of a conventional parallel-channel cold plate under the same conditions. Our study explores the effects of varying solid volume fractions, fluid directions, and multiple HBM configurations, and reveals the trade-offs between hotspot cooling, fluid pumping requirements, and thermal crosstalk. These results demonstrate that thermofluidic topology optimization enables optimal cold plate designs for thermal management of high-performance AI chips and heterogeneous packages.
Conventional die-bonding processes for High-Resolution Mini/Micro-LED (MLED) displays face critical challenges in simultaneously achieving high throughput and placement accuracy, which limits manufacturing yield and scalability. To address this issue, this study proposes and implements a needle-type high-speed precision die-bonding (HSP-DB) scheme equipped with a dedicated BIN wafer arrangement algorithm. The algorithm calculates optimal column and row arrangement pitches to maximize chip density on the BIN wafer while preventing interference and ensuring post expansion alignment with substrate pads. Compared to the conventional scheme, the HSP-DB process reduced the comprehensive placement misalignment for R, G, and B chips by 49.1%, 40.5%, and 39.3%, respectively, and increased the average bonding throughput by over 37%, from 38.2 Hz to 52.4 Hz. This work provides a feasible layout design framework for needle-type die-bonding process and offers an effective pathway toward high-accuracy, high-throughput mass manufacturing of Mini/Micro-LED displays.
The electro-thermal and mechanical interaction between MEMS vertical probes and fine-pitch interconnections governs probing reliability in advanced wafer-level testing. Although NiCo is widely used as a reference material, its performance is limited by Joule heating and contact-induced damage under high current and large overdrive. This study evaluates Cu–7 wt.%Ag (CuAg 7%) as an alternative probe material using a multi-model finite-element assessment that couples electro-thermal analysis, displacement-controlled contact, and high-cycle fatigue prediction. The framework combines a local contact model (285 μm) for AFM-validated indentation analysis and a guided cobra-type model for current-carrying capacity and bending-dominated fatigue assessment. The model considers DC currents of 0.1–1.0 A, probe lengths from 285 to 5000 μm under natural convection, and overdrive up to 50 μm applied to Al pads, SnAg solder balls, and Cu-filled TSVs. The contact model is validated against AFM probe-mark measurements with MAPE (Mean Absolute Percentage Error) of at least 35.02%. Under identical boundary conditions, CuAg 7% exhibits a substantially improved thermal margin compared with NiCo, with peak temperature remaining below 82 °C at 1.0 A and 2000 μm probe length, while NiCo exceeds 800 °C. CuAg 7% also reduces contact-induced deformation, yielding a solder-ball indentation depth of approximately 35.4 μm at 50 μm overdrive. High-overdrive solder-ball indentation is interpreted as a severe limiting case rather than an acceptable operating condition. Fatigue analysis identifies the knee region as the life-limiting location, with a minimum predicted fatigue life on the order of 1.15 × 105 cycles. These results indicate that CuAg 7% offers a balanced design compromise between thermal reliability, mechanical compliance, and fatigue performance, supporting its use as an alternative to NiCo for MEMS vertical probe tips in fine-pitch wafer-level testing.
This paper proposes a compressed parametric dynamic modeling framework for high-speed electronic systems based on Kernel Ridge Regression. The approach combines a NARX representation with a separable kernel that accounts for both dynamic input-output histories and external parameter variations. A Nyström-compressed formulation is introduced to handle the large training datasets generated by transient simulations while limiting the number of model coefficients. The method is assessed on three signal-integrity examples, ranging from IC-buffer modeling to high-speed interconnects with linear and non-linear terminations with multiple geometrical parameters. The results demonstrate accurate transient and eye-diagram prediction with reduced training time and model complexity.
