Semiconductor manufacturing is a resource and energy-intensive industry with a substantial environmental footprint. To address the footprint, we present a methodology for quantifying the environmental impact of semiconductor unit processes using the Environmental Footprint 3.1 Life Cycle Impact Assessment (LCIA) framework, focusing on identifying improvement opportunities in process steps with less sensitivity to defects. We apply this methodology to backside wet cleaning by proposing an alternative single-wafer process that adopts ozonated chemistries. The assessment used primary data from imec’s 300 mm pilot line. Results show that the proposed process reduces the total environmental footprint by 55% compared to the baseline Spin Cleaning with Repetitive use of Ozonated water and Diluted HF process. Key reductions include 67% less electricity for cleaning, 59% less HF use, and a 31% reduction in ultrapure water consumption. When scaled to a facility producing N28 Logic wafers at 50,000 wafer starts per month, with 46 backside clean steps per processed wafer, the process achieves annual savings of approximately 4 million kWh of electricity and 28 million liters (28,000 m3) of tap water per year. A sensitivity analysis revealed that replacing fossil-based electricity with hydroelectric power further reduces total environmental impacts by up to 63%, emphasizing the benefit of combining process innovation with renewable energy sourcing.

The telecommunications sector is experiencing rapid growth, driven by the exponential rise in data transmission volumes. This demand has led to significant innovation in the front-end-module, and particularly in the power amplifiers (PAs), requiring III–V group-based compound semiconductor materials, instead of traditional silicon-based technologies. ICT hardware manufacturing raises multiple sustainability concerns, including the intensive use of natural resources, significant waste generation, and the high consumption of electrical energy during production. These issues are further exacerbated by the rapid growth of the ICT market and the increasing shift toward non-silicon-based technologies. We address these issues in this paper through a comparative life cycle assessment (LCA) of the environmental impacts associated with the fabrication of PAs based on different semiconductor technologies suited for user equipment applications (45RFSOI, GaN-on-Si HEMT, GaAs HBT). We show a substantially higher impact per cm 2 in terms of climate change (∼1.6x higher) and resource depletion (∼470x higher) for the market-dominant GaAs PA compared to RFSOI and GaN-on-Si technologies. It is due to the GaAs wafer manufacturing and the usage of gold. In addition to LCA considerations, the integration of compound semiconductor materials introduces broader sustainability concerns, particularly with respect to resource scarcity, economic viability, and potential social implications. We explore these dimensions and highlight concerns related to gold usage in GaAs PA as well as different critical materials used in these radio frequency technologies.

Silicon wafers are the basis on which integrated circuit chips are produced. Hence, their constant supply is the backbone of digitalization. However, the silicon wafer supply chain is concentrated in a few geographic areas. This concentration makes the supply chain susceptible to unforeseen disruptions. This lack of resilience calls for a shift of silicon wafer supply towards Europe. Conversely, European Integrated Circuit chip manufacturers have to lower their Scope 3 emissions and, thus, the environmental impacts of their supply chain. This study investigates the environmental impacts of a global and a European silicon wafer supply chain scenario through regionalized Life Cycle Assessment. We modeled the supply chains using publicly available data. We show the most impactful suppliers and the differences in environmental impacts between a global and European silicon wafer supply chain through a contribution, hotspot, sensitivity, and uncertainty analysis. In our results, we highlight the effects and importance of regionalized Life Cycle Assessment for global, abiotic supply chains as well.

Metal halide perovskites have emerged as promising gain materials for thin-film laser diodes. However, achieving electrically excited amplified spontaneous emission (ASE) in perovskite light-emitting diodes (PeLEDs), a pre-condition for perovskite laser diodes, is hindered by the conflicting requirements of high conductivity and high net modal gain of the device stack. Here we develop a transparent PeLED architecture that combines low optical losses with excellent current-injection properties. Using 2.3 ns optical pulses at 77 K, we achieve ASE with a threshold of 9.1 μJ cm −2 . Upon submicrosecond electrical excitation at 77 K of the same device, we achieve current densities above 3 kA cm −2 with irradiance values above 40 W cm −2 . Notably, co-pumping the PeLED with optical pulses that are synchronized with the leading edge of an intense electrical pulse results in a reduction of the ASE threshold by 1.2 ± 0.2 μJ cm −2 , showing that electrically injected carriers contribute to optical gain. Furthermore, to assess the feasibility of a perovskite semiconductor optical amplifier, we probe the PeLED with 1-μs-long optical excitation and observe continuous-wave ASE at a threshold of 3.8 kW cm −2 . Finally, we show that such intense electrical pulses generate electroluminescence brightness levels close to half the irradiance produced by continuous-wave optical pumping at the ASE threshold. This work shows that perovskite semiconductor optical amplifiers and injection lasers are within reach using this type of transparent PeLED.

Future advanced semiconductor manufacturing processes are introducing significant patterning challenges. These challenges are coming together with additional requirements for sustainable, low Global Warming Potential/ low toxicity /low fine particle emissions. As a result, new solutions in terms of process integrations, molecules used for patterning modules, and overall stack of materials will have to meet those requirements while staying compatible with high-volume manufacturing (cost, availability, throughput, and overall patterning performance). Although specific process steps such as capacitor patterning for DRAM or 3D NAND high aspect ratio oxide etch are heavily scrutinized steps in terms of emissions and patterning challenges, many applications, including logic, integrate hundreds of steps where the patterning of 10-30 nm-thick layers requiring fluorine-containing gases. Although independently accounting for a modest amount of emissions, their sheer counts makes them a major contributor to CO2 equivalent emissions. In this work, the cumulative impact of these low aspect-ratio patterning steps will be modelled through the imec.netzero program model. Then, the impact of a few sustainability-optimized solutions, such as low temperature etching for ultra-thin layer or stack optimization will be assessed.

In order to incorporate environmental considerations into the decision criteria used to select substrates for radio-frequency integrated circuits (RF IC) technologies, we report here a comparative cradle-to-gate life cycle assessment (LCA) for Si and III-V state-of-the-art RF technologies. It appears that the global warming potential (GWP) of GaN-on-SiC is penalized by the high manufacturing energy of SiC wafers. Although less impactful than SiC, GaAs substrates show a higher GWP than Si-based technologies, which is also linked to an energy-intensive wafer fabrication. For GaN-on-Si, the epitaxy of the ~2.5 um-thick III-N layers represents an important part of the emissions making it ~30% more impactful than TR SOI substrates. In terms of abiotic depletion potential (ADP), the relatively large amount of Ga and As required to fabricate GaAs wafers leads to the highest ADP of all substrates. SiC also shows a high ADP due to the energy-intensive wafer fabrication. A significantly lower ADP is obtained for Si-based technologies.

Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography -both 193nm (DUV) and 13.5 nm (EUV) -has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel.

Electrode grids are used in neuroscience research and clinical practice to record electrical activity from the surface of the brain. However, existing passive electrocorticography (ECoG) technologies are unable to offer both high spatial resolution and wide cortical coverage, while ensuring a compact acquisition system. The electrode count and density are restricted by the fact that each electrode must be individually wired. This work presents an active micro-electrocorticography (µECoG) implant that tackles this limitation by incorporating metal oxide thin-film transistors (TFTs) into a flexible electrode array, allowing to address multiple electrodes through a single shared readout line. By combining the array with an incremental-ΔΣ readout integrated circuit (ROIC), the system is capable of recording from up to 256 electrodes virtually simultaneously, thanks to the implemented 16:1 time-division multiplexing scheme, offering lower noise levels than existing active µECoG arrays. In vivo validation is demonstrated acutely in mice by recording spontaneous activity and somatosensory evoked potentials over a cortical surface of ≈8×8 mm2 . The proposed neural interface overcomes the wiring bottleneck limiting ECoG arrays, holding promise as a powerful tool for improved mapping of the cerebral cortex and as an enabling technology for future brain-machine interfaces.

In this work, we present an all-solution fabrication approach for external second-order 1D distributed feedback (DFB) gratings using soft UV-nanoimprint lithography (UV-NIL) above archetypical methylammonium lead iodide (MAPbI3) perovskite films. This high-throughput method can be carried out in an ambient environment and requires only slightly elevated temperatures as low as 70 degrees C, gentle imprint pressure, and the use of compatible UV-NIL resin. Under stripe-shaped optical excitation, we observe simultaneously occurring optical phenomena in our high-gain strong-scattering perovskite films, namely amplified spontaneous emission, random lasing, and 1D DFB lasing. In pursuit of distinguishing these mechanisms, we explore far-field emission patterns and output polarization. Additionally, the DFB lasing is hardly attenuated when a thin absorbing indium tin oxide (ITO) film, commonly used as an electrode in fully contacted electrical devices, is inserted between the perovskite film and the DFB grating. As a result, we reproducibly achieve single and multimode, low-threshold (below 100 mu J center dot cm-2), narrow linewidth (below 0.2 nm), and strongly polarized (extinction ratio above 50) optically pumped DFB lasing for MAPbI3 waveguides with and without an adjacent ITO layer. We believe that the proposed resonator integration approach can be extended toward complete electrically active devices, enabling an alternative integration scheme to achieve current-injection lasing.

Sustainability is gaining momentum as countries and companies announce targets for net-zero carbon emissions by 2050. imec has created a bottom-up model using tool data, process recipes, and integrated wafer process flows to create a virtual fab. With this model, it is possible to quantify the environmental impact of manufacturing integrated circuit (IC) chips for current and future logic and memory technology modes. In this paper, the model is used to identify areas with the highest environmental impact. It is important to reduce the impact of both lithography and etch since together they are responsible for 45% of total CO2 equivalent emissions associated with fabricating an N3 logic node wafer. For lithography, two approaches to reducing the environmental impact will be described: one concentrates on tool consumption and the other on process choices to maximize throughput. For etch, the focus is on reducing overall gas consumption and improving wafer material stacks to minimize fluorocarbon use. Translating patterning process changes into emission numbers will enable informed process choices for future and contribute to a shift towards net-zero semiconductor manufacturing.

Unraveling the dominant charge transport mechanism in high-mobility amorphous oxide semiconductors is still a matter of controversy. In the present study we extended the random band-edge model suggested before for the charge transport and Hall-effect mobility in such disordered materials [Fishchuk et al., Phys. Rev. B 93, 195204 (2016)], and also describe the field-effect-modulated thermoelectricity in amorphous In-Ga-Zn-O ($a$-IGZO) films under the same premises. The model is based on the concept of charge transport through the extended states and assumes that the transport is limited by the spatial variation of the position of the band edge due to the disorder potential, rather than by localized states. The theoretical model is formulated using the effective medium approximation framework and describes well basic features of the Seebeck coefficient in disordered materials as a function of energy disorder, carrier concentration, and temperature. Carrier concentration dependencies of power factor and thermoelectric figure of merit have been also considered for such systems. Besides, our calculations reveal a remarkable turnover effect from a negative to a positive temperature dependence of Seebeck coefficient upon increasing carrier concentration. The suggested unified model provides a good quantitative description of available experimental data on the Seebeck coefficient and the charge mobilities measured in the same $a$-IGZO transistor as a function of the gate voltage and temperature by considering the same charge transport mechanisms. This promotes a deeper understanding and a more credible and accurate description of the transport process in $a$-IGZO films.

An extraction framework that can precisely reflect the metal-semiconductor contact behavior is developed for self-aligned top-gated oxide semiconductor field-effect transistors (SA-TG OS FETs). In contrast to the conventional transfer length method, where the extraction is performed at a constant drain voltage condition, an improved constant current scheme, resilient to bias-dependent series resistance, is employed to enhance the extraction accuracy. This technique enables one to unveil the underlying device physics at the metal-OS interface under top-gated operation. Furthermore, the resistance of contact and extension regions can be accurately differentiated by exploiting the extraction results from the three-terminal FETs and two-terminal resistors using the present framework. Moreover, the significant role of the specific contact resistivity at the metal-OS interface is highlighted as the dominating factor that detrimentally affects the electrical performance of OS FETs.

Active area scaling enables high operational stabilities and extreme brightness

We present variable-size circular micro methylammonium lead iodide PeLEDs and systematically examine their performance in moderate and high current density regimes. We demonstrate the beneficial influence of device downscaling on the internal heat generation and its positive impact on lifetime. For micron size glass-based devices with external quantum efficiencies (EQE) of around 5.5 %, we achieve a T50 > 5 h at 1000 mA·cm-2 at room temperature. The scaling-down approach and device architecture optimizations allowed for pulsed driving of the PeLEDs as short as 250 ns, reaching exceptionally large current densities above 5 kA·cm-2 and radiance values above 30000 W·m-2·sr-1.

The coming of age of AR, VR and MR applications and usage scenarios relies on the development of ever-improved advanced light management systems, both for sensing (camera) and actuation (display), e.g., solid-state dToF or FMCW scanning or flash LiDAR, polarimetric imaging or resettable structured light illumination for 3D mapping, directional imager for light field registration, plasmonic or dielectric color filters and directors for efficient spectroscopic information acquisition. Indeed, optics remains the dominant user interface modality while large portions of required information can be retrieved in optical domain. These systems rely on the emergence of mature mass-manufacturing integrated photonics platforms in near infrared and visible wavelength ranges. This presentation introduces developments at imec of diffractive components for reflective, transmissive and guided applications on opaque (Si/CMOS) and transparent (quartz) substrates, relying on sub-wavelength nano-patterning techniques (from DUV dry and wet (immersion) lithography through 200mm wafer-scale e-beam, nano-imprint lithography, block-co-polymer to EUV), novel CMOS-compatible material toolbox beyond Si and SiN (passive, active, resettable and tunable) and high-aspect ratio re-filling to enable stacking of optical features to define complex functional system. In particular, we will report on pixel-integrated Fresnel phase plates for local eQE optimization, on process complexity trade-off enabled by optical meta-materials, aspherical and non-cylindrical optical components for directed light, tunable structured light scanners, plasmonic and dielectric-based color filters and directors, optical beamformer in near infrared, sub-wavelength spatial light modulator in the visible and finally novel developments for 2D optical waveguides.

In an effort to fabricate In-Ga-Zn oxide (IGZO) thin-film transistors (TFTs) that combine high performance and high stability, we optimize sputtering conditions to create devices based on different IGZO phases: amorphous, c-axis-aligned crystalline (CAAC), and a transition between them, which is introduced here as protocrystalline IGZO. For this, we study the performance of TFTs based on thin films of IGZO sputtered at different substrate temperatures T-sub and oxygen flow ratios R-O2. While T-sub is the principal phase-determining parameter, R-O2 can be further optimized to enhance IGZO TFT characteristics. For both amorphous IGZO and CAAC IGZO, the best TFT performance and the best TFT bias stress stability are found under different sputtering conditions. In contrast, the protocrystalline IGZO shows a convergence of the highest TFT performance and the best bias stress stability, observed for an IGZO film sputtered at T-sub = 200 degrees C and R-O2 = 20%.

This paper analyzes the effect of high current under illumination stress (HCIS) in self-aligned amorphous indium gallium zinc oxide transistors with Al2O3 as high-kappa gate dielectric. A negative parallel threshold voltage (V-T) shift with the appearance of hysteresis (Delta V-hys) is observed after HCIS. In contrast to the double ionized oxygen vacancy (V-O(2+)) theory, a peroxide donor theory based on ab initio calculations is proposed to explain the degradation. Several methods are carried out to support the mechanism, including Delta V-hys generation, stress recovery behavior and capacitance-voltage (C-V) measurements. A linear dependence between initial V-T and negative V-T shift is observed that further supports the peroxide theory. This work highlights the importance of evaluating the HCIS for oxide base semiconductor devices.

We present dual‐gate (DG) dual‐layer (a‐ITZO and a‐IGZO) amorphous oxide TFTs integrated on polyimide (PI) foil. The fabricated TFTs show an apparent dual‐gate field‐effect mobility (µFE) of 45.0 cm2/ (V.s), sub‐threshold slope (SS−1) of 0.40 V/decade and ION/IOFF ratio of >108. The DG dual‐layer TFT based ring‐oscillators exhibit faster oscillation frequencies (fosc) compared to DG a‐IGZO TFT based ring‐oscillators. These TFTs are paving the way to faster scan drivers and higher resolution displays. It is also verified that with DG dual‐layer TFTs, the current variation can be reduced when applying an off‐panel compensation method to the asymmetric channel.

A light‐emitting transistor in which two gates, separated by an insulator, partially overlap in the center of the device is proposed. By accumulating charge carriers in dedicated transport layers, each gate independently controls charge injection into the emissive layer sandwiched between the transport layers. This structure combines the advantages of pinned light emission in the center of the channel, gapless charge transport into the recombination zone, and controlled balance of electron and hole concentration at the edges of the emissive layer for any chosen current density. High‐performance devices with overlapping gates are demonstrated: Using a red fluorescent emitter, high external quantum efficiency (5.7%) is conserved up to the highest luminance (2190 cd m −2 ). A comprehensive optoelectronic device model is proposed that verifies the measured characteristics and confirms that efficiency is highest with balanced charge transport. This device topology opens perspectives in the development of bright thin film light sources driven at high current densities.