Compound nerve action potentials (CNAPs) were used as a metric to assess the stimulation performance of a novel high-density, transverse, intrafascicular electrode in rat models. We show characteristic CNAPs recorded from distally implanted cuff electrodes. Evaluation of the CNAPs as a function of stimulus current and calculation of recruitment plots were used to obtain a qualitative approximation of the neural interface’s placement and orientation inside the nerve. This method avoids elaborate surgeries required for the implantation of EMG electrodes and thus minimizes surgical complications and may accelerate the healing process of the implanted subject.

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this article, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range, and electrode dc offset (EDO) cancellation. An ac-coupled 1st-order digitally-intensive $\Delta $ - $\Delta \Sigma $ architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits, and a digital control, has been fabricated in 22-nm fully depleted silicon on insulator (FDSOI) CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 $\mu \text{W}$ , and an input-referred noise of 7.7 ± 0.4 $\mu \text{V}_{\mathrm {rms}}$ in the AP band and 11.9 ± 1.1 $\mu \text{V}_{\mathrm {rms}}$ in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

Electrode grids are used in neuroscience research and clinical practice to record electrical activity from the surface of the brain. However, existing passive electrocorticography (ECoG) technologies are unable to offer both high spatial resolution and wide cortical coverage, while ensuring a compact acquisition system. The electrode count and density are restricted by the fact that each electrode must be individually wired. This work presents an active micro-electrocorticography (µECoG) implant that tackles this limitation by incorporating metal oxide thin-film transistors (TFTs) into a flexible electrode array, allowing to address multiple electrodes through a single shared readout line. By combining the array with an incremental-ΔΣ readout integrated circuit (ROIC), the system is capable of recording from up to 256 electrodes virtually simultaneously, thanks to the implemented 16:1 time-division multiplexing scheme, offering lower noise levels than existing active µECoG arrays. In vivo validation is demonstrated acutely in mice by recording spontaneous activity and somatosensory evoked potentials over a cortical surface of ≈8×8 mm2 . The proposed neural interface overcomes the wiring bottleneck limiting ECoG arrays, holding promise as a powerful tool for improved mapping of the cerebral cortex and as an enabling technology for future brain-machine interfaces.

In this paper, we present a miniature 128-channel neural recording IC (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs). An AC-coupled 1 st -order Δ-ΔΣ architecture is proposed to achieve rail-to-rail electrode DC offset rejection, low power and small area, while providing low noise and larger input range compared to other AC-coupled designs. This digitally-intensive architecture leverages the advantages of a highly-scaled technology node (22nm FD-SOI). The fabricated NRIC achieves a total area per channel of 0.005mm 2 , a total power per channel of 8.3μW, and an input-referred noise of 7.7±0.4μV rms in the AP band and 11.9±1.1μV rms in the LFP band. The chip has been fully validated in saline, demonstrating its capability to successfully record full-band neural signals.

Fundamental neuroscience research and high-performance neuro-prostheses require large-scale brain interfaces with ever-greater spatial resolution across a large cortex coverage, which cannot be achieved with current passive (micro) electrocorticography (ECoG) technologies. In this article, we present an active micro-electrocorticography ( $\mu $ ECoG) implant system that circumvents these challenges while achieving significantly lower noise compared to other existing active $\mu $ ECoG arrays. The proposed brain implant system is composed of a flexible, actively multiplexed 256-electrode $\mu $ ECoG array and an incremental- $\Delta \Sigma $ readout integrated circuit (ROIC). The 1 cm $\times $ 1 cm $\mu $ ECoG array was fabricated in a 3- $\mu \text{m}$ IGZO thin-film transistor (TFT) technology on a 15- $\mu \text{m}$ flexible foil and coupled to a 1.25 mm $\times $ 1.25 mm CMOS ROIC fabricated in a 22-nm fully depleted silicon on insulator (FDSOI) process. Due to the 256:16 time-division multiplexing achieved in the electrode array, only 16 multiplexed channels are required in the ROIC to acquire signals from the 256 electrodes simultaneously. By combining TFT multiplexing with newly proposed bulk-DAC (BDAC) feedback in the readout channel, we can integrate and address 4 $\times $ more electrodes than other passive arrays, achieve >10 $\times $ less noise than existing active arrays, and obtain >2 $\times $ effective channel area reduction in the ROIC while maintaining comparable electrical performance over current state-of-the-art ( $\mu $ )ECoG readouts.

Electrocorticography (ECoG) recording is a non-penetrating electrophysiology technique that achieves a good balance between spatial resolution, brain coverage and invasiveness [1]. For this reason, it is widely used for the diagnosis of neural disorders and holds promise for prosthetic applications. Although ECoG electrodes have been until recently quite large (~4mm diameter), several studies have shown that micro-scale electrodes (< 1mm diameter) are better suited for studying cortical pathology and implementing neural prostheses [2]. The design of flexible, high-density $\mu\mathsf{ECoG}$ arrays is challenging since every electrode must be individually addressed, resulting in a wiring bottleneck. Therefore, passive µECoG arrays have a limited electrode count and suffer from poor spatial coverage [3]. In contrast, active $\mu\mathsf{ECoG}$ arrays have emerged to provide higher spatial coverage with better spatial resolution. The most prominent active array [4] uses Si nanomembrane transistors to multiplex the electrodes and significantly reduce the signal routing. However, the source follower in this array severely limits its noise performance. Moreover, multiplexed $\mu\mathsf{ECoG}$ arrays impose additional design challenges on the readout IC (ROIC): i) compared to regular non-multiplexed ROICs [3], at least N times higher bandwidth (BW) is required (where N:1 is the multiplexing ratio); ii) the electrode DC offsets (EDOs) from N electrodes are modulated and cannot be removed with traditional AC coupling or DC servo loops (DSLs); and iii) sufficiently low noise is needed to compensate for the noise aliasing caused by the electrode multiplexing.

The recording of biopotential signals using techniques such as electroencephalography (EEG) and electrocardiography (ECG) poses important challenges to the design of the front-end readout circuits in terms of noise, electrode DC offset cancellation and motion artifact tolerance. In this paper, we present a 2(nd)-order hybrid-CTDT Delta n-ary sumation - n-ary sumation modulator front-end architecture that tackles these challenges by taking advantage of the over-sampling and noise-shaping characteristics of a traditional Delta n-ary sumation modulator, while employing an extra n-ary sumation -stage in the feedback loop to remove electrode DC offsets and accommodate motion artifacts. To meet the stringent noise requirements of this application, a capacitively-coupled chopper-stabilized amplifier located in the forward path of the modulator loop serves simultaneously as an input stage and an active adder. A prototype of this direct-to-digital front-end chip is fabricated in a standard 0.18-mu m CMOS process and achieves a peak SNR of 105.6 dB and a dynamic range of 108.3 dB, for a maximum input range of 720 mV(pp). The measured input-referred noise is 0.98 mu V-rms over a bandwidth of 0.5-100 Hz, and the measured CMRR is >100 dB. ECG and EEG measurements in human subjects demonstrate the capability of this architecture to acquire biopotential signals in the presence of large motion artifacts.

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled $\Delta $ - $\Delta \Sigma $ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm 2 per channel, an input-referred noise of 5.53 ± 0.36 $\mu \text{V}_{\mathrm{ rms}}$ in the action potential band and 2.88 ± 0.18 $\mu \text{V}_{\mathrm{ rms}}$ in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 $\text{M}\Omega $ . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm2 per channel, an input-referred noise of 5.53±0.36µVrms in the AP band and 2.88±0.18µVrms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.

An ultra-small-area, low-power analog front-end (AFE) for high-density neural recording is presented in this brief. It features an 11-bit incremental delta-sigma analog-to-digital converter ( $\Delta \Sigma $ ADC) enhanced with an offset-rejecting event-driven input biasing network. This network avoids saturation of the ADC input caused by leakage of the input-coupling capacitor implemented in an advanced technology node. Combining AC-coupling with direct data conversion, the proposed AFE can tolerate a rail-to-rail electrode offset and achieves a good trade-off between power, noise, bandwidth, input impedance, and area. Fabricated in a 22-nm fully-depleted silicon on insulator (FDSOI) process, the design occupies an active area of <0.001mm2, the smallest obtained to this date for a neural AFE, and consumes $\mathbf { < }3~\mu \text{W}$ from a 0.8-V supply. It achieves an input-referred noise of $11.3~\mu \text{V}_{\mathrm{ rms}}$ in the action potential band (300 Hz – 10 kHz) and 10 $\mu \text{V}_{\mathrm{ rms}}$ in the local field potential band (1 Hz – 300 Hz).

This paper presents a direct-digitalization front-end for wearable bio-signal recording. The proposed front-end is built with a 2 nd order hybrid-CTDT $\Delta \Sigma - \Sigma$ modulator, taking the benefits of oversampling and noise shaping. The $\Delta \Sigma - \Sigma$ topology removes electrode DC offset and shapes signals as well as motion artifacts at the input by adding $a\Sigma -$stage in the feedback loop, while the $\Sigma -$stage recovers the bio-signals by quantizing the difference of the consecutive samples. To meet the requirements of noise, input impedance of a bio-potential interface, a capacitively-coupled chopper amplifier serves as an input stage and also an active adder. An asynchronous 5-bit differential-difference SAR quantizer combines the functionalities of a coarse ADC and a passive adder in a traditional $\Delta \Sigma$ loop, leading to a compact output stage. The prototype IC is fabricated in a standard TSMC $0.18 \mu m$ CMOS process and achieves the peak SNR of 105.6dB and DR of 108.3dB with the maximum linear input range of 720mV pp . Its input referred noise is $0.98 \mu $ Vrms over 100Hz bandwidth. ECG and EEG measurements verify the bio-potential signals acquisition capability of this IC.

Within our internal FITEP technology platform (FITEP: Flexible Implantable Thin Electronic Package), a novel implantable packaging technology is under development in order to realize a very small, flexible, biomimetic package for electronic implants. This new platform enables a radical miniaturization of the final implanted device, which opens many new possibilities for the medical world, since it will be possible to insert electronic sensors in very small locations, such as arteries, nerves, glands,... The device encapsulation consists of a multilayer of biocompatible polymers and ultrathin ceramic diffusion barriers deposited using ALD techniques (ALD: atomic layer deposition) in order to fabricate a very thin and flexible but also highly hermetic device packaging. Concerning the selection of biocompatible polymers, polyimide can offer a profound mechanical support for the various device components, while Parylene with its excellent step coverage creates a highly conformal coating surrounding all components. Hermeticity can be realized by the use of ultrathin ceramic ALD layers such as Al2O3 and HfO2. An optimized ALD process will result in layers from very high quality with very good step coverage. As such, selected ALD layers of only a few tens of nm thick, can exhibit very low Water Vapor Transmission Rates (WVTR), making these ALD materials ideal as ultrathin diffusion barriers. The tested polyimide/ALD stack proved to be a very hermetic enclosure: copper patterns protected with the polyimide/ALD stack are still in perfect condition after more than 2 years of immersion in saline at 60 °C (test is still ongoing), while Cu patterns protected by the polyimide stack without ALD barriers showed first signs of damage already after 6 weeks exposure to saline. Platinum and gold are best suited for metallization of implanted electronics, but these noble metals do not adhere easily to polymers, hence dedicated measures to promote metal-polymer adhesion are essential. The FITEP platform is applied on a Si-probe for implantation in the peripheral nerves, consisting of a CMOS chip with recording and stimulation electrodes [Op de Beeck, M. 2017]. The chip is thinned down to 35um and packaged using polyimide and ALD multi-stacks, resulting in a 75um thin fully encapsulated chip, optimized to reduce the Foreign Body Reaction to obtain optimum electrode-nerve contact. Flexible interconnects are fabricated using gold and platinum sandwiched between polymers and ALD layers. For optimal charge injection, iridium oxide is used as electrode material. After this hermetic FITEP-based chip encapsulation, the CMOS chip is still fully functional, which was tested dry (in air) as well as during submersion in saline. First acute in vivo stimulation tests have shown good electrode stimulation capabilities. Mechanical bending tests on long 5um thick gold interconnects are performed, showing that even after up to 1.5 million bending cycles, no cracks occurred in the gold patterns (testing in air). Longer term immersion in saline and in-vivo testing showed some problems related to loss of adhesion and to galvanic effects of the metallization. These observations were leading to some improvements in the fabrication of the encapsulation. In a second packaging iteration of the CMOS chip, these improvements were realized and a new series of encapsulated devices is fabricated. First results are promising, showing improved metal adhesion. Longer term stability tests are on its way.

In this work, the development of an active high-density transverse intrafascicular micro-electrode (hd-TIME) probe to interface with the peripheral nervous system is presented. The TIME approach is combined with an active probe chip, resulting in improved selectivity and excellent signal-to-noise ratio. The integrated multiplexing capabilities reduce the number of external electrical connections and facilitate the positioning of the probe during implantation, as the most interesting electrodes of the electrode array can be selected after implantation. The probe chip is packaged using thin-film manufacturing techniques to allow for a minimally invasive electronic package. Special attention is paid to the miniaturization, the mechanical flexibility and the hermetic encapsulation of the device. A customized probe chip was designed and packaged using a flexible, implantable thin electronic package (FITEP) process platform. The platform is specifically developed for making slim, ultra-compliant, implantable complementary metal-oxide-semiconductor based electronic devices. Multilayer stacks of polyimide films and HfO2/Al2O3/HfO2 layers deposited via atomic layer deposition act as bidirectional diffusion barriers and are key to the hermetic encapsulation. Their efficacy was demonstrated both by water vapor transmission rate tests and accelerated immersion tests in phosphate buffered saline at 60 degrees C. Using the hd-TIME probe, an innovative implantation method is developed to prevent the fascicles from moving away when the epineurium is pierced. In addition, by transversally implanting the hd-TIME probe in the proximal sciatic nerve of a rat, selective activation within the nerve was demonstrated. The FITEP process platform can be applied to a broader range of integrated circuits and can be considered as an enabler for other biomedical applications.

Although MOS-based pseudo-resistors are capable of achieving the ultra-high resistance required to design small-area neural amplifiers, they suffer from substrate leakage currents which become dramatically higher when the devices are exposed to light. This can cause unwanted amplifier offsets and hinders the usability of these devices in the emerging optoelectrical neural applications. A solution is proposed to compensate the pseudo-resistor leakage current using a dummy deep N-well device. Experimental results show that neural amplifiers implemented with the compensated pseudo-resistor become more robust to photo-induced leakage currents.

It is an uninformative truism to state that the brain operates at multiple spatial and temporal scales, each with each own set of emergent phenomena. More worthy of attention is the point that our current understanding of it cannot clearly indicate which of these phenomenological scales are the significant contributors to the brain’s function and primary output (i.e. behaviour). Apart from the sheer complexity of the problem, a major contributing factor to this state of affairs is the lack of instrumentation that can simultaneously address these multiple scales without causing function altering damages to the underlying tissue. One important facet of this problem is that standard neural recording devices normally require one output connection per electrode. This limits the number of electrodes that can fit along the thin shafts of implantable probes generating a limiting balance between density and spread. Sharing a single output connection between multiple electrodes relaxes this constraint and permits designs of ultra-high density probes. Here we report the design and in-vivo validation of such a device, a complementary metal-oxide-semiconductor (CMOS) scanning probe with 1344 electrodes; the outcome of the European research project NeuroSeeker. We show that this design targets both local and global spatial scales by allowing the simultaneous recording of more than 1000 neurons spanning 7 functional regions with a single shaft. The neurons show similar recording longevity and signal to noise ratio to passive probes of comparable size and no adverse effects in awake or anesthetized animals. Addressing the data management of this device we also present novel visualization and monitoring methods. Using the probe with freely moving animals we show how accessing a number of cortical and subcortical brain regions offers a novel perspective on how the brain operates around salient behavioural events. Finally, we compare this probe with lower density, non CMOS designs (which have to adhere to the one electrode per output line rule). We show that an increase in density results in capturing neural firing patterns, undetectable by lower density devices, which correlate to self-similar structures inherent in complex naturalistic behaviour. To help design electrode configurations for future, even higher density, CMOS probes, recordings from many different brain regions were obtained with an ultra-dense passive probe.

Charge balancing has been often considered as one of the most critical requirement for neural stimulation circuits. Over the years several solutions have been proposed to precisely balance the charge transferred to the tissue during anodic and cathodic phases. Elaborate dynamic current sources/sinks with improved matching, and feedback loops have been proposed with a penalty on circuit complexity, area or power consumption. Here we review the dominant assumptions in safe stimulation protocols, and derive mathematical models to determine the effectiveness of passive charge balancing in a typical application scenario.

Advanced bionic prosthetics that can restore both the motor functionality and sensory perception of an amputee, require high-resolution recording and stimulation interfaces targeting the peripheral nervous system (PNS). To provide high nerve fiber selectivity, we propose a low-noise (3.67 mu Vrms), low-power (2.24mW) and high-density CMOS microelectrode probe for intra-neural implantation. The probe is composed of two ICs, encapsulated in a biocompatible and hermetic package, each featuring 64 recording and 16 stimulation electrodes. A backend IC digitizes the recorded signals at 31.25kS/s and provides spike detection.

We present a high electrode density and high channel count CMOS (complementary metal-oxide-semiconductor) active neural probe containing 1344 neuron sized recording pixels (20 µm × 20 µm) and 12 reference pixels (20 µm × 80 µm), densely packed on a 50 µm thick, 100 µm wide, and 8 mm long shank. The active electrodes or pixels consist of dedicated in-situ circuits for signal source amplification, which are directly located under each electrode. The probe supports the simultaneous recording of all 1356 electrodes with sufficient signal to noise ratio for typical neuroscience applications. For enhanced performance, further noise reduction can be achieved while using half of the electrodes (678). Both of these numbers considerably surpass the state-of-the art active neural probes in both electrode count and number of recording channels. The measured input referred noise in the action potential band is 12.4 µVrms, while using 678 electrodes, with just 3 µW power dissipation per pixel and 45 µW per read-out channel (including data transmission).