This paper proposes a novel pre-coding method that enables bypassing the soldering reflow issue in resistive memory devices called RRAM. This method is based on the difference between forming and set voltages distributions to discriminate virgin memory cells from those in which data were pre-coded before the soldering step. This procedure enables data recovery through the application of a voltage pulse over the whole memory array. This method, demonstrated on bipolar HfO 2 -based resistive elements, can be extended to all RRAM devices that exhibit a significant margin between forming and set voltages distributions.

In Flash-like memory technologies, the replacement of the continuous polysilicon gate by silicon nanocrystals enables improving reliability thanks to discrete charge trapping within nanocrystals. In this context, this paper deals with the extraction of some physical parameters on silicon nanocrystals dedicated to non-volatile memories. An optimized industrial “full silane” process was used to grow nanometric crystals on top of a tunnel oxide. Various “in-line” and “off-line” imaging techniques such as Atomic Force Microscopy, Scanning Electron Microscopy and Transmission Electron Microscopy were advantageously deployed to extract some physical parameters such as average size, density, or coverage of silicon nanocrystals.

This paper deals with the role of platinum or titanium–titanium nitride electrodes on variability of resistive switching characteristics and electrical performances of HfO2-based memory elements. Capacitor-like Pt/HfO2 (10nm)/Pt and Ti/HfO2 (10nm)/TiN structures were fabricated on top of a tungsten pillar bottom electrode and integrated in-between two interconnect metal lines. First, quasi-static measurements were performed to apprehend the role of electrodes on electroforming, set and reset operations and their corresponding switching parameters. Memory elements with Pt as top and bottom electrodes exhibited a non-polar behavior with sharp decrease of current during reset operation while Ti/HfO2/TiN capacitors showed a bipolar switching behavior, with a gradual reset. In a second step, statistical distributions of switching parameters (voltage and resistance) were extracted from data obtained on few hundreds of capacitors. Even if the resistance in low resistive state and reset voltage was found to be comparable for both types of electrodes, the progressive reset operation observed on samples with Ti/TiN electrodes led to a lower variability of resistance in high resistive state and concomitantly of set voltage. In addition Ti–TiN electrodes enabled gaining: (i) lower forming and set voltages with significantly narrower capacitor-to-capacitor distributions; (ii) a better data retention capability (10years at 65°C instead of 10years at 50°C for Pt electrodes); (iii) satisfactory dynamic performances with lower set and reset voltages for ramp speed ranging from 10−2 to 107V/s. The significant improvement of switching behavior with Ti–TiN electrodes is mainly attributed to the formation of a native interface layer between HfO2 oxide and Ti top electrode.

This paper demonstrates the feasibility of resistive switching memory elements integrating a nickel oxide film deposited on top of a pillar bottom electrode. The unipolar switching was investigated over a wide temperature range (25 to 125°C) on samples integrating either W or Cu plugs with diameters ranging from 1 down to 0.18μm. The switching characteristics and scaling trends of various fabricated memory elements were compared to select the best bottom electrode contact. It was shown that NiO layers deposited on top of W-plugs exhibited the most satisfactory electrical characteristics for future high density memory devices. Their reliability performances in terms of endurance and retention were subsequently studied by using either quasi-static or pulse programming modes. Set operations with short (10 to 20ns) and low amplitude (around 2V) voltage pulses were also demonstrated.

The present paper deals with the bipolar resistive switching of memory elements based on metal–organic complex CuTCNQ (copper-7,7’,8,8’-tetracyanoquinodimethane) nanowires grown on a dedicated HfO2 oxide switching layer. Switching characteristics are explored either at millimeter scale on pad-size devices or at nanoscale by using conductive atomic force microscopy. Whatever the investigation scales, the basic memory characteristics appear to be controlled by copper ionic transport within a switching layer. This latter corresponds to either HfO2 layer in pad-size devices or nanogap formed at nanoscale between the atomic force microscopy conductive tip and CuTCNQ surface. Depending upon the observation scale, the switching layer (either HfO2 oxide or nanogap) acts as a matrix in which copper conductive bridges are formed and dissolved thanks to redox processes controlled in alternating applied bias voltages.

Integration of functional materials in memory architectures leads to emerging concepts with disruptive performances as compared to conventional charge storage technologies. Beside floating gate solutions such as EEPROM and Flash, these alternative devices involve voltage or current-controlled switching mechanisms between two distinct resistance states. The origin of the resistance change straightforwardly depends upon the nature and fundamental physical properties of functional materials integrated in the memory cell. After a general overview of non volatile memories, this paper is focused on prototypical and emerging memory cells and on their ability to withstand a downscaling of their critical dimensions. In addition, despite different maturity levels, a peculiar attention is turned toward common guidelines helpful for designing embedded or distributed resistive switching memory circuits.

Non-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges. Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2. In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM.

In this paper, a peculiar attention is turned towards the understanding of the current overshoot occurring during the forming operation in resistive switching memory devices. This phenomenon is attributed to the discharge of a parasitic capacitance in parallel to the resistive device in simple 1R (one resistor, no transistor/diode selector) architectures. The impact of such an overshoot is analyzed on both NiO and HfO2-based memory elements by performing measurements with different setups (quasi-static and pulse measurements). We show that the parasitic event is more severe as the forming voltage in the memory device increases. Moreover, it is shown that the post-forming resistance cannot be simply adjusted by a current compliance available on semiconductor parameter analyzers, since this internal limiter is ineffective in the microsecond range for compliance levels lower than the current spike. The current overshoot playing a detrimental role on the electrical performances of resistive devices, it must be carefully monitored when assessing the electrical performances in simple 1R architectures.

In this paper, we show the coexistence of the bipolar and unipolar resistive-switching modes in NiO cells realized using an optimized oxidation process of a Ni blanket layer used as the bottom electrode. The two switching modes can be activated independent of the cell switching history provided the appropriate programming conditions are applied. The bipolar and unipolar switching modes are discussed as driven by electrochemical- and thermal-based mechanisms, respectively. The switching versatility between these two modes is demonstrated both for large oxidized Ni films and for Ni films oxidized at the bottom of small dimension contact holes. The perspective of selecting the desired switching mode in a scaled device made in a small diameter single hole is highly attractive because the specific advantages of the two modes broaden the application scope of the cell and enable larger flexibility in terms of memory architecture.

Powders and thin films of ferroelectric Bi3.25La0.75Ti3O12 (BLT) have been prepared from a sol-gel precursor heated at various temperatures, up to 600 degrees C. The BLT precursor and the BLT powders have been characterized by thermal analyses, X-ray diffraction (XRD), scanning and transmission electron microscopy (SEM and TEM). Then, the precursor has been used to deposit thin films of ferroelectric BLT on specific silicon substrates, using a specific spin coating process. The thin films have been characterized by XRD, SEM and ellipsometry. Electrical polarization analyses have been finally performed on these films, and performing remnant polarization has been obtained.

As Flash memories are approaching their ultimate scaling limit, reversible resistance switching attracts considerable interest because of its potential for high density non volatile memory devices. Resistive switching phenomena have been reported in many transition metal oxide films such as TiO 2 or MO. This work investigates the feasibility of emerging resistive- switching devices with NiO active dielectric layer on top of a pillar W bottom electrode. Reversible and repetitive switching is demonstrated for ReRAM cells with diameters ranging from 0.18 to 1 mum. Scaling and cycling capabilities are discussed and preliminary TEM results enable apprehending reliability issues and failure mechanisms.

Emerging concepts of non-volatile memories are more and more investigated to replace conventional charge storage-based devices like EEPROM or Flash. One of these promising memory concepts is called Resistive Switching Memory (ReRAM). Such memory is based on a switching mechanism controlled in current and/or voltage, between two distinct resistive states depending upon the material nature integrated in memory element. To lead such memory concept to a memory circuit or even, to a product, a big effort has to be done to forecast tools necessary to design and test this emerging memory. In this paper, a particular technology of ReRAM memories is introduced. First, an electrical model (ELDO-like) of a MIM-based (Metal/Insulator/Metal) ReRAM memory element is presented. Then, this model is used for the robustness assessment of ReRAM memory element in presence of actual defects inherent to CMOS process steps. Based on this electrical model, a big hurdle has been broken between material physics, design and test. Thus, new methods and solutions could be developed in the field of design and test for ReRAM memories.

The NiO resistive-switching memory is under investigation due to its attractive properties and scaling potential. In this paper, we evidence the possible coexistence of both the bipolar and unipolar switching modes in NiO films. The bipolar mode can be activated provided the oxidation time is limited so that O 2- movement through easy paths allows electrochemical reduction/oxidation, while the unipolar mode is favored for longer oxidation times associated with larger NiO cell resistance. The memory states in bipolar and unipolar modes are shown to have different electrical properties.

Films of a catalytic compound (RuO2) were deposited by spin-coating process on ferroelectric films mainly constituted of SrBi2Ta2O9 (SBT) and Ba2NaNb5O15 (BNN) phases. SBT films were deposited by MOCVD method, and BNN films were deposited by sputtering. After thermal treatment under air, these ferroelectric-catalytic systems were characterized by X-ray diffraction and scanning electron microscopy (SEM). SEM images showed that RuO2 film morphology depended on substrate nature. A study of CH4 conversion into CO2 and H2O was carried out using these catalytic-ferroelectric multilayers: the conversion was analyzed from Fourier Transform Infrared (FT-IR) spectroscopy, at various temperatures. Improved catalytic properties were observed for RuO2 films deposited on BNN oxide layer.

Conventional memories approaching their scaling limit, reversible resistance switching effects attract considerable attention because of the potential for high density non volatile memory devices. These resistive switching phenomena have been reported in many simple transition metal oxide films such as TiO2 or NiO deposited by standard sputtering techniques. This paper is investigating the feasibility of emerging resistive-switching stacks enabling integration of the memory element in interconnect structures resulting in very small memory cells. Indeed, we have developed innovative process steps leading to localized formation of bi-stable NiO at the bottom of via structures. Thickness-controlled NiO layers were formed from the partial oxidation of blanket Ni metallic layer through via holes opened in SiO2. Reversible and repetitive switching was demonstrated on arrays of vias with diameter down to 150 nm. Besides, encouraging reliability performances in terms of endurance and retention were obtained.

Resistance switching is an interesting alternative to conventional charge storage devices for future high density storage media. Cu/CuTCNQ(300 nm)/Al memory structures with pad size ranging from 1000 down to 150 ¿m were carefully studied to apprehend their switching behavior. Electrical testing revealed bipolar resistive switching and a shrink of the memory window as the pad-size decreased. Current in low resistance state (LRS) was demonstrated as top pad area dependent. Besides, to investigate their potential scaling, local current measurements performed by conductive-AFM demonstrated the switching of CuTCNQ films at a nanometer scale with a discrimination window of 3 decades between high and low resistance states. Current mappings and local current-voltage characteristics were measured to study the statistical and spatial distribution of switching regions over the CuTCNQ thin film.

Resistive switching controlled by external voltage has been reported in many Metal/Resistive oxide/Metal (MRM) structures in which the resistive oxide was simple transition metal oxide thin films such as NiO or TiO2 deposited by reactive sputtering. In this paper, we have explored the possibility to form NiO-based MRM structures from the partial oxidation of a blanket Ni metallic film using a Rapid Thermal Annealing route, the remaining Ni layer being used as bottom electrode. X-ray diffraction was used to apprehend the Ni oxidation kinetics while transmission electron microscopy enabled investigating local microstructure and film interfaces. These analyses have especially emphasized the predominant role of the as-deposited Ni metallic film microstructure (size and orientation of crystallites) on (i) oxidation kinetics, (ii) NiO film microstructural characteristics (crystallite size, texture and interface roughness) and (iii) subsequent electrical behavior. On this latter point, the as-grown NiO films were initially in the low resistance ON state without the electro-forming step usually required for sputtered films. Above the threshold voltage varying from 2 to 5 V depending on oxidation conditions, the Pt/NiO/Ni MRM structures irreversibly switched into the high resistance OFF state. This irreversibility is thought to originate in the microstructure of the NiO films that would cause the difficulty to re-form conductive paths. (C) 2007 Elsevier B.V All rights reserved.

The oxidation characteristics of TiAlN films integrated in the bottom electrode (BE) stack of three-dimensional SrBi2Ta2O9-based (SBT) ferroelectric capacitors are investigated in the range of 650–800°C. The patterned TiAlN\Ir\IrO2\Pt BE is encapsulated by a thin ferroelectric SBT film deposited by metal organic chemical vapor deposition and then crystallized ex situ at temperatures higher than 650°C in oxygen. During this annealing step the TiAlN film oxidizes from the lateral side of the patterned BE mesas. Compared to the vertical oxidation in blanket TiAlN layers, the lateral oxidation rate in our capped patterned films is much larger for similar oxidation conditions. This lateral oxidation of the TiAlN is strongly correlated with the in-film SBT stress that depends upon the deposition temperature and the thickness of the SBT film: the higher the tensile stress in the SBT, the larger the TiAlN oxidation length induced. From a kinetic study, the lateral oxygen diffusion was found to be a self-limited process with activation energy of about 2.2eV and a preexponential factor D0 of 7×10−3cm2∕s. This factor, one to two orders of magnitude higher than the one obtained in blanket TiAlN layers, is indicative of interfacial diffusion. The mechanism of the increased lateral oxidation can be understood by the high tensile stress of the SBT film at the sidewall of the ferroelectric capacitors that tends to tear apart the Ir∕TiAlN interface and causes enlarged interfacial oxygen diffusion. The limiting step of the oxidation mechanism is identified as oxygen diffusion in the Al-depleted∕Ti-rich TiAlN layer that lies beyond the Al-rich film found at the very edge of the capacitors, whereas on blanket films the oxygen diffusion is limited in the Al-rich surface layer region.

Catalytic ruthenium dioxide films were deposited by spin-coating process on ferroelectric films mainly constituted of SrBi2Ta2O9 (SBT) and Ba2NaNb5O15 (BNN) phases. After thermal treatment under air, these ferroelectric–catalytic systems were characterized by X-ray diffraction and scanning electron microscopy (SEM). SEM images showed that RuO2 film morphology depended on substrate nature. A study of CH4 conversion into CO2 and H2O was carried out using these catalytic–ferroelectric multilayers: the conversion was analyzed from Fourier transform infrared (FTIR) spectroscopy, at various temperatures. Improved catalytic properties were observed for RuO2 films deposited on BNN oxide layer.

Future development of Ferroelectric Random Access Memories (FeRAM) requires integration of three-dimensional (3D) ferroelectric capacitors in replacement of usual planar capacitors. This innovative geometry enables the fabrication of highly reliable memory devices with improved sensing signal. In order to target space applications, it is of primary interest to analyze the effects of ionizing radiations (x-rays, X-rays...) on capacitors integrated in advanced memory architectures. In this paper, effects of x-rays combined with either bias voltage or bipolar electrical cycling were analyzed on 3D ferroelectric capacitor memory-like arrays. Using an experimental setup enabling measurements under radiations, these arrays were submitted to electrical stresses simulating the various states of the memory. For memory-like arrays in "written" state (no applied bias), high dose of X-rays accelerates both fatigue-like (polarization reduction) and imprint-like (voltage shift) phenomena, which may subsequently alter normal memory operations. Nevertheless, it has been shown that repeated cycling makes the degradation mechanisms reversible. Alternatively, for memory-like arrays in "writing" state, two distinct simulated conditions have been considered. If irradiated capacitors are always being written in the same state, huge and irreversible imprint-like effect may cause memory cell "read" or "write" failures. Moreover, if capacitors are cycled in normal conditions (i e. bipolar pulses), the strong acceleration of fatigue mechanism may cause "read" failures since the two remnant states may be indistinguishable during memory reading.