The aim of the research is to develop a material thickness measurement method to monitor oxide polishing by Chemical-Mechanical Planarization (CMP) during the realization of the Shallow Trench Isolation (STI). The underlying goal is to build a statistical regulation model of the polishing time on a single platen (the two others platens are monitored by an endpoint signal). In addition to the process parameters (head sweep, platen, and head rotation velocity), input and output polished material thicknesses data are essential to build a run-to-run model for CMP. Therefore, stack layer thickness, before and after polishing, needs to be measured fast enough to maintain the acceptable throughput and to accurately control the polishing time wafer by wafer. In this paper, we describe how spectroscopic reflectometry embedded in the polishing equipment, can meet rapidity and capability requirements in setting up a run-to-run control algorithm to maintain the target thickness for STI CMP.

The aim of the research is to develop a material thickness measurement method to monitor oxide polishing by Chemical-Mechanical Planarization (CMP) during the realization of the Shallow Trench Isolation (STI). The underlying goal is to build a statistical regulation model of the polishing time on a single platen (the two others platens are monitored by an endpoint signal). In addition to the process parameters (head sweep, platen, and head rotation velocity), input and output polished material thicknesses data are essential to build a run-torun model for CMP. Therefore, stack layer thickness, before and after polishing, needs to be measured fast enough to maintain the acceptable throughput and to accurately control the polishing time wafer by wafer. In this paper, we describe how spectroscopic reflectometry embedded in the polishing equipment, can meet rapidity and capability requirements in setting up a run-to-run control algorithm to maintain the target thickness for STI CMP.

In this study, the focus is made on interferometry endpoint detection for Shallow Trench Isolation (STI) Chemical Mechanical Planarization (CMP) process done on the first platen of the tool for a three platen-polishing configuration. The interferometry principle is based on light interferences produced by thin transparent and semitransparent layers. Thus the removed thickness can be correlated to the intensity measured over time. The optical signal received during the SiO2 removal is affected by patterned wafers and pattern type. For STI stack, parameters like Gap Fill SiO2 thickness, trench depth, pattern density and surface topology, could be involved in laser light diffraction and scattering. In some cases, these unwanted effects are stronger than the periodical signal of the removed SiO2 layer thus, preventing from endpoint algorithm usage. A correlation analysis has been performed based on experimental data between memory product layouts parameters and the response of raw signal detection. It confirms that the more sizable the Electrically Erasable Programmable Read-Only Memory (E2PROM) coverage is, the weaker and noisier the signal is. However, our experiment also shows that regardless of the SiO2 thickness, a deeper trench will produce a more exploitable signal. In conclusion, perspectives for future experimentations are explored, in order to set up CMP optical endpoint detection by interferometry for a broader type of memory device patterns. Keywords: Planarization, Chemical-mechanical Polishing, optical endpoint, interferometry, STI CMP, device pattern.

An experimental methodology compliant with industrial constraints was deployed to uncover the origin of soft breakdown events in large planar silicon-based NMOS capacitors. Complementary advanced failure analysis techniques were advantageously employed to localize, isolate and observe structural defects at nanoscale. After an accurate localization of the failing area by optical beam-induced resistance change (OBIRCH), focused ion beam (FIB) technique enabled preparing thin specimens adequate for transmission electron microscopy (TEM). Characterization of the gate oxide microstructure was performed by high-resolution TEM imaging and energy-filtered spectroscopy. A dedicated experimental protocol relying on iterative FIB thinning and TEM observation enabled improving the quality of electron imaging of defects at atom scale. In that way, the gate oxide integrity was evaluated and an electrical stress-induced silicon epitaxy was detected concomitantly to soft breakdown events appearing during constant voltage stress. The growth of silicon hillocks enables consuming a part of the breakdown energy and may prevent the soft breakdown event to evolve towards a hard breakdown that is catastrophic for device functionality.

In Flash-like memory technologies, the replacement of the continuous polysilicon gate by silicon nanocrystals enables improving reliability thanks to discrete charge trapping within nanocrystals. In this context, this paper deals with the extraction of some physical parameters on silicon nanocrystals dedicated to non-volatile memories. An optimized industrial “full silane” process was used to grow nanometric crystals on top of a tunnel oxide. Various “in-line” and “off-line” imaging techniques such as Atomic Force Microscopy, Scanning Electron Microscopy and Transmission Electron Microscopy were advantageously deployed to extract some physical parameters such as average size, density, or coverage of silicon nanocrystals.