High Density Advanced Package Design - or HDAP - continues to show remarkable advantages over monolithic SoC. Foundries and OSATs are teaming to provide manufacturing capabilities including FOWLP and various derivatives suitable for RF, IoT, automotive and mobile products or SI 3D 3DIC designs typically used in today's advanced memory and GPU/CPU applications. As HDAP manufacturing advances, so does design complexity requiring clearly defined and understood design methodologies. After providing an analysis the key steps to perform complex HDAP design including component aggregation, assembly and system optimization and design verification, this paper will highlight the requirement for a "shift-left" design environment where verification steps including LVS & LVL, thermal, power and signal integrity are performed interactively during the system integration and optimization and not left to after design completion.

Silicon photonics is nothing new. It has been around for decades, but in recent years, it has gained traction as electronic design challenges increase drastically with their atomic-level limitations. Silicon photonics has made significant advancements during this period, but there are many obstacles without an acceptable level of comfort as seen by the lack of semiconductor community involvement. Apart from a series of technological barriers, such as extreme fabrication sensitivity, inefficient light generation on-chip, etc., there are also certain design challenges. In this chapter, we will discuss the challenges and the opportunities in photonic integrated circuit design software tools, examine existing design flows for photonics design and how these fit different design styles, and review the activities in collaboration and standardization efforts to improve design flows.

Electronic circuit designers commonly start their design process with a schematic, namely an abstract representation of the physical circuit. In integrated photonics on the other hand, it is very common for the design to begin at the physical component level. In order to build large integrated photonic systems, it is crucial to design using a schematic-driven approach. This includes simulations based on schematics, schematic-driven layout, layout versus schematic verification, and post-layout simulations. This paper describes such a design framework implemented using Mentor Graphics and Lumerical Solutions design tools. In addition, we describe challenges in silicon photonics related to manufacturing, and how these can be taken into account in simulations and how these impact circuit performance.

This paper describes design methodologies developed for silicon photonics integrated circuits. The approach presented is inspired by methods employed in the Electronics Design Automation (EDA) community. This is complemented by well established photonic component design tools, compact model synthesis, and optical circuit modelling. A generic silicon photonics design kit, as described here, is available for download at http://www.siepic.ubc.ca/GSiP.

To improve the design flow for silicon and other photonics technologies, companies from the photonics [1, 2] and electronics design automation [3] domain collaborate, to improve the integration of simulations, layout, verification and design rule checking.

Silicon photonics has become a promising technology for photonic integrated circuits. During the past few years, there has been a dramatic increase in the scale and complexity of silicon photonic circuits, which introduces many new design challenges and creates a need for efficient and standardized design flows. We have developed a complete design flow that combines mature electronic design automation (EDA) software with optical simulation software. This flow makes it possible to reliably design, simulate, layout and manufacture large-scale silicon photonic circuits in a unified environment.

Broad adoption of silicon photonics technology for photonic integrated circuits requires standardized design flows that are similar to what is available for analog and mixed signal electrical circuit design. We have developed a design flow that combines mature electronic design automation (EDA) software with optical simulation software. An essential component of any design flow, whether electrical or photonic, is the ability to accurately simulate largescale circuits. This is particularly important when the behavior of the circuit is not trivially related to the individual component performance. While this is clearly the case for electronic circuits consisting of hundreds to billions of transistors, it is already becoming important in photonic circuits such as WDM transmitters, where signal cross talk needs to be considered, as well as optical cross-connect switches. In addition, optical routing to connect different components requires the introduction of additional waveguide sections, waveguide bends, and waveguide crossings, which affect the overall circuit performance. Manufacturing variability can also have dramatic circuit-level consequences that need to be simulated. Circuit simulations must rely on compact models that can accurately represent the behavior of each component, and the compact model parameters must be extracted from physical level simulation and experimental results. We show how large scale circuits can be simulated in both the time and frequency domains, including the effects of bidirectional and, where appropriate, multimode and multichannel photonic waveguides. We also show how active, passive and nonlinear individual components such as grating couplers, waveguides, splitters, filters, electro-optical modulators and detectors can be simulated using a combination of electrical and optical algorithms, and good agreement with experimental results can be obtained. We then show how parameters, with inclusion of fabrication process variations, can be extracted for use in the circuit level simulations. Ultimately, we show how a multi-channel WDM transceiver can be created, from schematic design to tapeout, using key features of EDA design flows such as schematic driven layout, design rule checking and layout versus schematic.