The relaxation mechanism of Si1-xGex/Si heterostructures subjected to pulsed laser melting was investigated by probing the pulsed laser induced epitaxy (PLIE) regime of undoped 20 nm Si0.5Ge0.5/Si thin films. The pseudomorphic “critical thickness” and evolution of bi-layer formation was determined as a function of average Ge concentration of the films via quantitative analysis of (004) HRXRD rocking curves. Comparison of pseudomorphic thicknesses alongside SIMS analysis reveals a “dynamic critical Ge concentration” of 27-30% Ge as the PLIE limit for pseudomorphic growth that is independent of average Ge concentration of the films. Plan-view weak-beam dark-field imaging revealed that surface dislocation half-loops are the primary strain relieving defects that reach concentrations on the order of 1010 cm−2. It is theorized that quasi-cellular solidification leads to lateral Ge segregation, creating nm scale localized regions of Ge pile-up and stress concentration. The morphology of the liquid/solid interface along with stress localization is what allows for the dislocation half-loop to be the primary strain relieving defect, with <110> edge defects acting as secondary. These results are important for understanding the conditions and strategies necessary to utilize pulsed laser melting to its fullest potential in applications towards pMOS source/drain contact engineering.

Nanosecond pulsed laser annealing using a frequency doubled Nd:YAG laser (lambda = 532 nm) was performed on undoped implant amorphized Si and 40 nm Si1-xGex epitaxial thin films ranging from x = 0.1 to 0.5. Ge+ implants were used to create similar to 15 nm thick surface amorphous layers. The microstructural evolution of the layers was investigated for laser powers that ranged from the sub-melt, partial amorphous layer melt, full amorphous layer melt, to full epi-layer melt regimes. Time resolved reflectometry and transmission electron microscopy was used to couple the impact of melt dynamics with resulting microstructures and to determine processing benchmarks as a function of Ge concentration. It was shown that for the right combination of power and amorphous layer thickness, defect free regrowth is possible. At melt depths >= 22 nm for the Si0.7Ge0.3 films, it was found that progressive liquid/solid interface roughening during solidification led to lateral germanium segregation coupled with the formation of dislocation half loops and dislocation loop clusters at the surface. These results are important for the exploration of pulsed laser melting of Si1-xGex for CMOS source/drain contact and channel strain engineering applications.

Conformal damage-free doping is the holy grail for 3D semiconductor device structures, such as those used in multi-gate and nanowire-based field effect transistors (FETs). The shape, dimension, pitch, and spacing of parallel conduction paths introduce increased complexity in a number of ways, but particularly in the area of intentional impurity introduction for doping. To this end, gas-phase doping using tertiarybutylarsine (TBA) was employed to dope silicon-on-insulator (SOI) thin films based circular transfer length measurement (CTLM) devices with top silicon thicknesses down to 4.5 nm, and substrate-released horizontal Si nanowires. Dopant incorporation was observed with a peak active carrier concentration of similar to 7 x 10(19) cm(-3) after a 1050 degrees C rapid thermal anneal (RTA). An optimisation study showed that dopant incorporation is similar for varying exposure times to TBA gas, while increased exposure can cause roughening of the Si due to etching. Structural analysis by cross-sectional transmission electron microscopy (XTEM) and Energy-dispersive X-ray spectroscopy (EDX) showed conformal formation of an As-rich surface oxide on free standing nanowires, without surface etching or crystal damage, making this process promising for future gate-all-around (GAA) transistor architectures.

This paper presents the application of monolayer doping (MLD) to silicon-germanium (SiGe). This study was carried out for phosphorus dopants on wafers of epitaxially grown thin films of strained SiGe on silicon with varying concentrations of Ge (18%, 30%, and 60%). The challenge presented here is achieving dopant incorporation while minimizing strain relaxation. The impact of high temperature annealing on the formation of defects due to strain relaxation of these layers was qualitatively monitored by cross-sectional transmission electron microscopy and atomic force microscopy prior to choosing an anneal temperature for the MLD drive-in. Though the bulk SiGe wafers provided are stated to have 18%, 30%, and 60% Ge in the epitaxial SiGe layers, it does not necessarily mean that the surface stoichiometry is the same, and this may impact the reaction conditions. X-ray photoelectron spectroscopy (XPS) and angle-resolved XPS were carried out to compare the bulk and surface stoichiometry of SiGe to allow tailoring of the reaction conditions for chemical functionalization. Finally, dopant profiling was carried out by secondary ion mass spectrometry to determine the impurity concentrations achieved by MLD. It is evident from the results that phosphorus incorporation decreases for increasing mole fraction of Ge, when the rapid thermal annealing temperature is a fixed amount below the melting temperature of each alloy.

Silicon (Si) has been scaled below 10 nm in multigate and silicon-on-insulator (SOI) device technologies, but clearly Si thickness cannot be reduced indefinitely, as we will run out of atoms eventually. As thickness approaches 5 nm, surfaces and interfaces will significantly impact the electrical behavior of Si, and surface physics cannot be discounted. Below that, bulk material properties will be altered considerably in the few-monolayer limit. One of the most basic defining properties of a semiconductor is its conductivity. To improve conductivity, while inducing a channel by appropriate biasing, it is necessary to define an accurate impurity doping strategy to reduce parasitic resistance. In this paper, we investigated the changing electrical conductivity of SOI films as a function of the Si thickness, in the range of 3–66 nm. SOI films were ex situ doped using three different approaches: liquid/vapor phase monolayer doping of phosphorus using allyldiphenylphosphine, gas-phase doping of arsenic using arsine (AsH3), and room-temperature beam-line ion implantation of phosphorus. The circular transfer length method and micro-four-point probe measurements were used to determine the resistivity of the Si films, mitigating the contribution from contact resistance. The resistivity of the Si films was observed to increase with decreasing Si film thickness below 20 nm, with a dramatic increase observed for a Si thickness at 4.5 nm. This may drastically impact the number of parallel conduction paths (i.e., nanowires) required in gate-all-around devices. Density functional theory modeling indicates that the surface of the Si film with a thickness of 4.5 nm is energetically more favorable for the dopant atom compared to the core of the film.

This paper details the application of phosphorus monolayer doping of silicon on insulator substrates. There have been no previous publications dedicated to the topic of MLD on SOI, which allows for the impact of reduced substrate dimensions to be probed. The doping was done through functionalization of the substrates with chemically bound allyldiphenylphosphine dopant molecules. Following functionalization, the samples were capped and annealed to enable the diffusion of dopant atoms into the substrate and their activation. Electrical and material characterisation was carried out to determine the impact of MLD on surface quality and activation results produced by the process. MLD has proven to be highly applicable to SOI substrates producing doping levels in excess of 1 × 1019 cm−3 with minimal impact on surface quality. Hall effect data proved that reducing SOI dimensions from 66 to 13 nm lead to an increase in carrier concentration values due to the reduced volume available to the dopant for diffusion. Dopant trapping was found at both Si–SiO2 interfaces and will be problematic when attempting to reach doping levels achieved by rival techniques.

Dopant incorporation in Si can be done in situ during epitaxial growth, or ex situ for localised material modification from a variety of sources including ion, solid, liquid, or gas. Gas-phase doping has the advantage that it does not require a thin film deposition, it is more effective at entering tight spaces than a liquid, and it is less damaging and more conformal than a beam-line ion implant. In this work, we apply arsine (AsH3) gas at approximately atmospheric pressures in order to n-type dope three-dimensional (3D) Si device structures. It was observed that the gas-phase doping can be either corrosive or gentle to thin-body Si depending on the process conditions. Initial doping processes caused damage to the Si due to etching, but after process optimisation, the structural integrity of the Si nanostructures could be maintained successfully. Moreover, it was noted that evaluating doping processes entirely on planar Si surfaces can be misleading: processes which appear promising initially may not be transferrable to non-planar thin-body structures like fins or nanowires, due to unwanted Si etching. Overall, we found that gas-phase doping with AsH3 could provide >1020 cm−3 electrically active As concentrations. This high As incorporation makes gas-phase doping very attractive for future gate-all-around devices, where the space between features will decline with continued transistor scaling.

The advent of high surface-to-volume ratio devices has necessitated a revised approach to parameter extraction and process evaluation in field-effect transistor technologies. In this work, active doping concentrations are extracted from the electrical analysis of Si nanowire devices with high surface-to-volume ratios. Nanowire resistance and Si resistivity are extracted, by first extracting and subtracting out the contact resistance. Resistivity (q) is selected as the benchmark parameter to compare different doping processes with each other. The impacts of nanowire diameter scaling to 10 nm and of nanowire spacing scaling to <20 nm are extracted for monolayer doping and beam-line ion implantation. Despite introducing significant crystal damage, P beam-line ion implantation beats allyldiphenylphosphine (ADP) P monolayer doping with a SiO2 cap in terms of lower Si resistivity and higher dopant activation, with dependencies on the nanowire width greater than on nanowire spacing. Limitations in ADP P monolayer doping with a SiO2 cap are due to the difficulties in dopant incorporation, as it is based on in-diffusion, and P atoms must overcome a potential barrier on the Si surface. Published by AIP Publishing.

As devices continue to shrink there is interest in the possibility of using compound semiconductors to replace Si and Ge for certain parts of the transistor. InAs and InGaAs are of particular interest. The contact resistance issue continues to be one of the largest challenges to future devices. In order to minimize contact resistance it is critical that the doping of the semiconductor be maximized in the contact regions. The best n-type dopant to date for InGaAs has been silicon. We have studied a number of methods of introducing Si including implantation and MBE doping. After annealing all samples saturate at the same doping level of around 1.5 x 1019/cm3. Several models have been proposed in the past to explain the saturation of Si doping in GaAs. These include the concept of a solid solubility and saturation through precipitate formation, the amphoteric nature of Si and self-compensation through the formation of SiGa - SiAs pairs and finally the possibility of compensation through the formation of vacancies, which bind to the active Si making a SiGa-VGa pair. This talk will review a number of recent studies exploring the highly unusual doping and diffusion behavior of Si In InGaAs. Epitaxial-grown [001] In0.53Ga0.47As samples were either implanted with silicon at 80°C, or the Si doping was grown into the InGaAs. The peak concentration values were > 5×1019 cm-3 in both cases. The samples were capped with 15nm of Al2O3 by ALD to prevent surface degradation and annealed between 550°C and 750°C. The activation and diffusion studies show that the precipitation model does not explain the observed diffusion behavior. A set of co-implant experiments comparing Al and P co-implants show that there are no notable changes in activation from co-implanting elements. The self-compensation model does not explain the observed results and it also does not explain the diffusion behavior. In addition co-implants with Sulfur also do not support the self-compensation model. This leaves the third explanation of a vacancy complex. Prior InGaAs and GaAs DFT calculations suggest that the negatively charged vacancy-Si pair is the primary contributor for Si diffusion in InGaAs. Modeling of the diffusion of Si in InGaAs requires an unusual point defect population that can be explained if there is a decrease in the formation energy for vacancies coupled with percolation theory for reduced migration energy of the vacancies. Vacancy formation can explain doping saturation, the diffusion behavior, the co-implant results. Finally implant damage was studied by TEM. It is shown that the implant defects are extrinsic and thus much like implants into bulk silicon there is an excess of interstitials associated with the implant process. These interstitials are shown to reduce the diffusivity of Si in InGaAs. As a final test defects are intentionally introduced into Si doped regions and their behavior is consistent with a vacancy rich region existing around the diffusing silicion. All these experiments are systematically compared to the proposed models and it is shown that only the vacancy complex model can explain all of the observed results. THus it is suggested that the formation of vacancy complexes is the reason for satuation of Si doping in InGaAs.As devices continue to shrink there is interest in the possibility of using compound semiconductors to replace Si and Ge for certain parts of the transistor. InAs and InGaAs are of particular interest. The contact resistance issue continues to be one of the largest challenges to future devices. In order to minimize contact resistance it is critical that the doping of the semiconductor be maximized in the contact regions. The best n-type dopant to date for InGaAs has been silicon. We have studied a number of methods of introducing Si including implantation and MBE doping. After annealing all samples saturate at the same doping level of around 1.5 x 1019/cm3. Several model have been proposed in the past to explain the saturation of doping of Si in GaAs. These include the concept of a solid solubility and saturation through precipitate formation, the amphoteric nature of Si and self-compensation through the formation of SiGa SiAs pairs and finally the possibility of compensation through the formation of vacancies, which bind to the active Si making a SiGa-VGa pair. This talk will also review a number of recent studies exploring the highly unusual doping and diffusion behavior of Si In InGaAs. Epitaxial-grown [001] In0.53Ga0.47As samples were either implanted with silicon at 80°C, or the Si doping was grown into the InGaAs. The peak concentration values were > 5×1019 cm-3 in both cases. The samples were capped with 15nm of Al2O3 by ALD to prevent surface degradation and annealed between 550°C and 750°C. The activation and diffusion studies show that the precipitation model does not explain the observed diffusion behavior. A set of co-implant experiments comparing Al and P co-implants show that there are no notable changes in activation from co-implanting elements. The self-compensation model does not explain the observed results and it also does not explain the diffusion behavior. In addition co-implants with Sulfur also do not support the self-compensation model. This leaves the third explanation of a vacancy complex. Prior InGaAs and GaAs DFT calculations suggest that the negatively charged vacancy-Si pair is the primary contributor for Si diffusion in InGaAs. Modeling of the diffusion of Si in InGaAs requires an unusual point defect population that can be explained if there is a decrease in the formation energy for vacancies coupled with percolation theory for reduced migration energy of the vacancies. Vacancy formation can explain doping saturation, the diffusion behavior, the co-implant results. Finally implant damage was studied by TEM. It is shown that the implant defects are extrinsic and thus much like implants into bulk silicon there is an excess of interstitials associated with the implant process. These interstitials are shown to reduce the diffusivity of Si in InGaAs. As a final test defects are intentionally introduced into Si doped regions and their behavior is consistent with a vacancy rich region existing around the diffusing silicion. All these experiments are systematically compared to the proposed models and it is shown that only the vacancy complex model can explain all of the observed results. THus it is suggested that the formation of vacancy complexes is the reason for satuation of Si doping in InGaAs.

There is significant research interest in the behavior of silicon as a dopant in InGaAs during processing conditions for possible integration into future CMOS devices. A major objective is obtaining low resistances for source and drain regions, which require very high doping concentrations near the limits of solid solubility (>1×1020cm-3). Understanding dopant behavior and activation near these limits are of paramount importance in order to fully integrate InGaAs and related III-V materials into systems previously dominated by silicon. In this work, a Si diffusion and activation model in In0.53Ga0.47As using the Florida Object Oriented Process and Device Simulator (FLOOXS) will be presented. Similar to previous studies in GaAs, the group-III vacancy-Si pair is implemented as the principle mechanism for silicon diffusion in InGaAs. Fermi level considerations concerning concentration-dependent diffusion are also taken into account in the presented model, building upon simpler previous models. Experimental studies that provided the data include Si-implanted InGaAs samples and MBE-grown delta-doped layers of Si in InGaAs. Both sets of samples were capped with Al2O3 and annealed at temperatures ranging from 550 to 750°C. As indicated through SIMS data, post annealed profiles for silicon exhibit very sharp shoulders characteristic of concentration dependent diffusion. The extracted power of concentration dependence from the SIMS results are relatively high (greater than n=4). This sharp dependence differs from prior continuum-based modelling procedures, where power dependence is believed to closely correspond to the charge state of defects responsible for diffusion. Ultimately the connection between diffusion and activation will be explored, along with developments in prediction and modelling. Figure 1

The thermal stability of Si dopants incorporated during growth and via ion implantation was investigated as a function of annealing time and temperature. Ion implanted samples show a maximum achievable doping concentration of 1.4×1019 cm-3. Growth doped samples exhibit higher post growth electrical activations than achievable in ion implanted samples but subsequent thermal processing at 750°C for 10 minutes is shown to deactivate heavily doped (3×1019 cm-3) MBE doped substrates to the same active doping concentration of 1.4×1019 cm-3 suggesting a common thermodynamic limit to Si activation in InGaAs.

Abstract not Available.