As metallic nanostructures shrink towards the size of the electronic mean free path, thermal conductivity decreases due to increased electronic scattering rates. Matthiessen's rule is commonly applied to assess changes in electron scattering rates, although this rule has not been validated experimentally at typical operating temperatures for most of the electronic systems (e.g., near room temperature). In this study, we experimentally evaluate the validity of Matthiessen's rule in determining the thermal conductivity of thin metal films by measuring the in-plane thermal conductivity and electronic scattering rates of copper (Cu) films with varying thicknesses (27 nm - 5 µm), microstructures, and grain boundary segregation. Comparing total electron scattering rates measured with infrared ellipsometry to infrared ultrafast pump-probe measurements, we find that the electron-phonon coupling factor is independent of film thickness, whereas the total electronic scattering rate increases with decreasing film thickness. Our findings provide experimental validation of Matthiessen's rule for electron transport in thin metal films at room temperature and also introduce an approach to discern critical heat transfer processes in thin metal interconnects, which holds significance for the advancement of future CMOS technology.

Subtractive ruthenium interconnects are being researched as a metallization scheme to replace damascene Cu in tight pitch interconnect layers. Its main advantages are better resistance scalability than Cu with decreasing dimensions, the ability to achieve high aspect ratios, and its compatibility with airgap. In this paper, we present R&D results obtained in a 3-layer stack test vehicle with standard performance and defectivity structures, which include resistance (R) and capacitance (C) benefits, as well as defect densities for via chains and leakage combs. In addition, we identify key performance enhancement factors that decrease Ru resistance by up to 15%. Furthermore, we report a robust next-via landing process on a subtractive Ru layer with airgap, capable of providing 25% of line-to-line capacitance reduction.

3-D stacked CMOS transistors offer an opportunity to enable further standard cell and SRAM scaling, making them a promising transistor architecture to extend Moore's law. We review state-of-the-art approaches for achieving 3-D CMOS stacking. The sequential approach is highlighted by fabricating Ge PMOS stacked via layer transfer on top of Si NMOS, and self-aligned approach is demonstrated by simultaneously fabricated NMOS-on-PMOS multi-nanoribbon Si transistors. Both approaches showcase a well-balanced CMOS inverter built from transistors in top and bottom device layers.

Nanomultilayers are complex architectures of materials stacked in sequence with layer thicknesses in the nanometer range. Their application in microelectronics is challenged by their thermal stability, conductivity, and interface reactivity, which can compromise their performance and usability. By using different materials as thermal barriers and by changing their thickness, it is possible to manipulate interfacial effects on thermal transport. In this work, we report on the thermal conductivity of Cu/W, Cu/Ta, and Cu/TaN sputter deposited nanomultilayers with different thicknesses. The resistive interfacial effects are rationalized and discussed also in relation to the structural transformation into a nano-composite upon high-temperature annealing.

A process to achieve 6 nm minimum dimension interconnect wires is realized using standard 193 nm lithography. Various metals including copper are optimized to gap fill features, and tested for electrical performance and reliability. Measurements showing line electrical resistance and electromigration as functions of material, conducting area, and interfaces are presented.

A sidewall planar capacitor (SW CAP) vehicle is developed to closely simulate processing conditions for metal barrier and dielectric in an integrated structure. For a known tantalum barrier for copper on a low-K dielectric, SW CAP TDDB is similar to those measured on an integrated vehicle. SW CAP results are useful for comparing electrical reliability of different dielectric systems, and effective in determining physical continuity of copper metal barriers.

Commonly known in macroscale mechanics, buckling phenomena are now also encountered in the nanoscale world as revealed in today's cutting-edge fabrication of microelectronics. The description of nanoscale buckling requires precise dimensional and elastic moduli measurements, as well as a thorough understanding of the relationships between stresses in the system and the ensuing morphologies. Here, we analyze quantitatively the buckling mechanics of organosilicate fins that are capped with hard masks in the process of lithographic formation of deep interconnects. We propose an analytical model that quantitatively describes the morphologies of the buckled fins generated by residual stresses in the hard mask. Using measurements of mechanical properties and geometric characteristics, we have verified the predictions of the analytical model for structures with various degrees of buckling, thus putting forth a framework for guiding the design of future nanoscale interconnect architectures.

Assessing metal gap fill capability and electrical behavior in patterned features ahead of full integration is valuable in interconnect process development as feature sizes scale beyond the 14 nm technology node. In this work a simple device is fabricated with existing silicon patterning recipes to achieve an electrical test vehicle that can test a range of metal candidates for interconnects. The vehicle is characterized using electron microscopy and electrical measurements.

The RC delay and power restrictions imposed by the interconnect system can contribute to poor circuit performance in an increasingly severe manner as dimensions shrink. Resistances are increasing faster than the scale factor of the technology and capacitance improvements are constrained by mechanical requirements of the assembled stack. Collectively, these cause a bottleneck in both local and global information transfer on a chip. Novel deposition methods and novel conductor materials are being explored as means to increase conductive cross sectional area. Molecular ordering is an opportunity to simultaneously deliver capacitance and mechanical strength. Despite these improvement paths, a more holistic approach to interconnect design is needed, where the application and micro architecture are more tolerant of RC scaling constraints.

The first part of this study examined oxide stability and cleaning of Ru surfaces. The surface reactions during H2 plasma exposure of Ru polycrystalline films were studied using x-ray photoelectron spectroscopy (XPS). The ∼2 monolayer native Ru oxide was reduced after H-plasma processing. However, absorbed oxygen, presumably in the grain boundaries, remains after processing. A vacuum thermal anneal at 150 °C substantially removes both surface oxide and absorbed oxygen which is attributed to a reduction by carbon contamination. The second part of the study examined the thermal stability of Cu on a Ru layer. The thermal stability or islanding of the Cu film on the Ru substrate was characterized by in situ XPS. After plasma cleaning of the Ru adhesion layer, the deposited Cu exhibited full coverage. In contrast, for Cu deposition on the Ru native oxide substrate, Cu islanding was detected and was described in terms of grain boundary grooving and surface and interface energies. The oxygen in the grain boundary has a negligible contribution to the surface energy and does not contribute to Cu islanding.