A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm 2 and operated up to 1 Gb/s at 1.2 V.

Since the first demonstration of a production quality three-dimensional (3D) stacked-word-line NAND Flash memory [1], the 3b/cell 3D NAND Flash memory has seen areal density increases of more than 50% per year due to the aggressive development of 3D-wordline-stacking technology. This trend has been consistent for the last three consecutive years [2-4], however the storage market still requires higher density for diverse digital applications. A 4b/cell technology is one promising solution to increase bit density [5]. In this paper, we propose a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput. The chip achieves a 5.63Gb/mm2 areal density, which is a 41.5% improvement as compared to a 3b/cell NAND Flash memory in the same 3D-NAND technology [4].

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm 2 with 53.2 MB/s of program throughput.

Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

This paper presents a novel CMOS readout circuit for satellite infrared time delay and integration (TDI) arrays. An integrate-while-read method is adopted, and a dead-pixel-elimination circuit for solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is proposed to improve the signal-to-noise ratio (SNR) for low-temperature targets. The readout circuit was fabricated with a 0.35-mu m CMOS process for a 500 x 4 mid-wavelength infrared (MWIR) HgCdTe detector array. Using the circuit, a 90% background-limited infrared photodetection (BLIP) is satisfied over a wide input range (similar to 200-330 K), and the SNR is improved by 11 dB for the target temperature of 200 K.

This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6µm standard CMOS process for a 150×64 CdTe X-ray detector array. The readout circuit was found to effectively increase the charge storage capacity up to 1.6×108 electrons, providing an improved SNR by a factor of approximately 8. The measured equivalent noise charge resulting from the readout circuit was 1.68×104 electrons, a negligible value compared to the shot noise from the detector.

A monolithic 64Gb MLC NAND flash based on 21nm process technology has been developed for the first time. The device consists of 4-plane arrays and provides page size of up to 32KB. It also features a newly developed DDR interface that can support up to the maximum bandwidth of 400MB/s. To address performance and reliability, on-chip randomizer, soft data readout, and incremental bit line precharge scheme have been developed.

A readout circuit incorporating a pixel level analog-to-digital converter (ADC) is studied for 2-D long wavelength infrared focal plane arrays (LWIR FPAs). The charge handling capacity of the unit cell circuit is improved by using the current input incremental ADC. The proposed pixel level ADC is based on an extended counting ADC but is composed of two oversampling conversions. The readout circuit has been fabricated using a 0.35 mu m 2-poly 4-metal CMOS process for a 128 x 128 LWIR HgCdTe array with a pixel size of 50 mu m x 50 mu m. The peak signal-to-noise ratio (S/N) and dynamic range (DR) were measured to be 85.8 dB and 99.9 dB, respectively, with a total power consumption of 50 mW.